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 | 2012 | |
|---|---|---|
| 7 |      | Ji Gu, Tohru Ishihara: A Case Study of Energy-efficient Loop Instruction Cache Design for Embedded Multitasking Systems. SMARTGREENS 2012: 197-202 |
| 2011 | ||
| 6 |  | Ji Gu, Hui Guo: Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems. IJHCR 2(4): 42-58 (2011) |
| 5 | | Ji Gu, Hui Guo, Patrick Li: An on-chip instruction cache design with one-bit tag for low-power embedded systems. Microprocessors and Microsystems - Embedded Hardware Design 35(4): 382-391 (2011) |
| 2010 | ||
| 4 | | Ji Gu, Hui Guo: Enabling large decoded instruction loop caching for energy-aware embedded processors. CASES 2010: 247-256 |
| 2009 | ||
| 3 | | Ji Gu, Hui Guo: A Segmental Bus-invert Coding Method for Instruction Memory Data Bus Power Efficiency. ISCAS 2009: 137-140 |
| 2 | | Ji Gu, Hui Guo, Patrick Li: ROBTIC: An On-chip Instruction Cache Design for Low Power Embedded Systems. RTCSA 2009: 419-424 |
| 1 | | Ji Gu, Hui Guo: An Efficient Segmental Bus-Invert Coding Method for Instruction Memory Data Bus Switching Reduction. EURASIP J. Emb. Sys. 2009: (2009) |
| 1 | Hui Guo | [1] [2] [3] [4] [5] [6] |
| 2 | Tohru Ishihara | [7] |
| 3 | Patrick Li | [2] [5] |
Colors in the list of coauthors
Last update Thu May 31 18:55:10 2012 CET by the DBLP Team —
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