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| 2012 | ||
|---|---|---|
| 43 | Gabi Sarkis, Warren J. Gross: Efficient Stochastic Decoding of Non-Binary LDPC Codes with Degree-Two Variable Nodes. IEEE Communications Letters 16(3): 389-391 (2012) | |
| 2011 | ||
| 42 | Camille Leroux, Ido Tal, Alexander Vardy, Warren J. Gross: Hardware architectures for successive cancellation decoding of polar codes. ICASSP 2011: 1665-1668 | |
| 41 | Camille Leroux, Alexandre J. Raymond, Gabi Sarkis, Ido Tal, Alexander Vardy, Warren J. Gross: Hardware Implementation of Successive Cancellation Decoders for Polar Codes CoRR abs/1111.4362: (2011) | |
| 40 | Ali Naderi, Shie Mannor, Mohamad Sawan, Warren J. Gross: Delayed Stochastic Decoding of LDPC Codes. IEEE Transactions on Signal Processing 59(11): 5617-5626 (2011) | |
| 39 | Matthieu Arzel, Cyril Lahuec, Christophe Jégo, Warren J. Gross, Y. Bruned: Stochastic Multiple Stream Decoding of Cortex Codes. IEEE Transactions on Signal Processing 59(7): 3486-3491 (2011) | |
| 38 | Saeed Sharifi Tehrani, Ali Naderi, Guy-Armand Kamendje, Shie Mannor, Warren J. Gross: Tracking Forecast Memories for Stochastic Decoding. Signal Processing Systems 63(1): 117-127 (2011) | |
| 2010 | ||
| 37 | François D. Côté, Ioannis N. Psaromiligkos, Warren J. Gross: On the code tracking performance of GNSS modulation. CISS 2010: 1-5 | |
| 36 | Francois Leduc-Primeau, Saied Hemati, Shie Mannor, Warren J. Gross: Lowering Error Floors Using Dithered Belief Propagation. GLOBECOM 2010: 1-6 | |
| 35 | Vincent C. Gaudet, Warren J. Gross: Switching Activity in Stochastic Decoders. ISMVL 2010: 167-172 | |
| 34 | Camille Leroux, Ido Tal, Alexander Vardy, Warren J. Gross: Hardware architectures for Successive Cancellation Decoding of Polar Codes CoRR abs/1011.2919: (2010) | |
| 33 | Camille Leroux, Saied Hemati, Shie Mannor, Warren J. Gross: Stochastic Chase Decoding of Reed-Solomon Codes. IEEE Communications Letters 14(9): 863-865 (2010) | |
| 32 | Kevin Cushon, Camille Leroux, Saied Hemati, Shie Mannor, Warren J. Gross: A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding. IEEE Trans. on Circuits and Systems 57-II(11): 893-897 (2010) | |
| 31 | Saeed Sharifi Tehrani, Chris Winstead, Warren J. Gross, Shie Mannor, Sheryl L. Howard, Vincent C. Gaudet: Relaxation dynamics in stochastic iterative decoders. IEEE Transactions on Signal Processing 58(11): 5955-5961 (2010) | |
| 30 | Quang Trung Dong, Matthieu Arzel, Christophe Jégo, Warren J. Gross: Stochastic Decoding of Turbo Codes. IEEE Transactions on Signal Processing 58(12): 6421-6425 (2010) | |
| 29 | Saeed Sharifi Tehrani, Ali Naderi, Guy-Armand Kamendje, Saied Hemati, Shie Mannor, Warren J. Gross: Majority-based tracking forecast memories for stochastic LDPC decoding. IEEE Transactions on Signal Processing 58(9): 4883-4896 (2010) | |
| 2009 | ||
| 28 | Bharathram Sivasubramanian, Warren J. Gross, Harry Leib: Design and FPGA implementation of iterative decoders for codes on graphs. CCECE 2009: 1080-1084 | |
| 27 | Francois Leduc-Primeau, Saied Hemati, Warren J. Gross, Shie Mannor: A Relaxed Half-Stochastic Iterative Decoder for LDPC Codes. GLOBECOM 2009: 1-6 | |
| 26 | Saeed Sharifi Tehrani, Ali Naderi, Guy-Armand Kamendje, Shie Mannor, Warren J. Gross: Tracking Forecast Memories in stochastic decoders. ICASSP 2009: 561-564 | |
| 25 | Gabi Sarkis, Shie Mannor, Warren J. Gross: Stochastic Decoding of LDPC Codes over GF(q). ICC 2009: 1-5 | |
| 24 | Kevin Cushon, Warren J. Gross, Shie Mannor: Bidirectional interleavers for LDPC decoders using transmission gates. SiPS 2009: 232-237 | |
| 23 | Christophe Jégo, Warren J. Gross: Turbo decoding of product codes using adaptive belief propagation. IEEE Transactions on Communications 57(10): 2864-2867 (2009) | |
| 22 | Jahyun J. Koo, Alan C. Evans, Warren J. Gross: 3-D Brain MRI Tissue Classification on FPGAs. IEEE Transactions on Image Processing 18(12): 2735-2746 (2009) | |
| 2008 | ||
| 21 | Andrew J. Wong, Warren J. Gross: Configurable Flow Models for FPGA Particle Graphics Engines. FCCM 2008: 283-284 | |
| 20 | Yousef El-Kurdi, David Fernández, Evgueni Souleimanov, Dennis Giannacopoulos, Warren J. Gross: FPGA architecture and implementation of sparse matrix-vector multiplication for the finite element method. Computer Physics Communications 178(8): 558-570 (2008) | |
| 19 | Shaoqiang Bi, Warren J. Gross: The Mixed-Radix Chinese Remainder Theorem and Its Applications to Residue Comparison. IEEE Trans. Computers 57(12): 1624-1632 (2008) | |
| 18 | Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gross: Fully Parallel Stochastic LDPC Decoders. IEEE Transactions on Signal Processing 56(11): 5692-5703 (2008) | |
| 17 | Saeed Sharifi Tehrani, Christophe Jégo, Bo Zhu, Warren J. Gross: Stochastic Decoding of Linear Block Codes With High-Density Parity-Check Matrices. IEEE Transactions on Signal Processing 56(11): 5733-5739 (2008) | |
| 16 | John Sachs Beeckler, Warren J. Gross: Particle graphics on reconfigurable hardware. TRETS 1(3): (2008) | |
| 2007 | ||
| 15 | Jahyun J. Koo, David Fernández, Ashraf Haddad, Warren J. Gross: Evaluation of a High-Level-Language Methodology for High-Performance Reconfigurable Computers. ASAP 2007: 30-35 | |
| 14 | Jahyun J. Koo, Alan C. Evans, Warren J. Gross: Accelerating a Medical 3D Brain MRI Analysis Algorithm using a High-Performance Reconfigurable Computer. FPL 2007: 11-16 | |
| 13 | Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gross: Survey of Stochastic Computation on Factor Graphs. ISMVL 2007: 54 | |
| 12 | Laurier Boulianne, Michel Dumontier, Warren J. Gross: A stochastic particle-based biological system simulator. SCSC 2007: 794-801 | |
| 11 | Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gross: An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding. SiPS 2007: 255-260 | |
| 10 | Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak: Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed-Solomon Decoding. IEEE Trans. VLSI Syst. 15(3): 309-318 (2007) | |
| 2006 | ||
| 9 | Yousef El-Kurdi, Warren J. Gross, Dennis Giannacopoulos: Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs. FCCM 2006: 293-294 | |
| 8 | Saeed Sharifi Tehrani, Warren J. Gross, Shie Mannor: Stochastic decoding of LDPC codes. IEEE Communications Letters 10(10): 716-718 (2006) | |
| 7 | Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak: Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes. IEEE Transactions on Communications 54(6): 1143 (2006) | |
| 6 | Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak: Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes. IEEE Transactions on Communications 54(7): 1224-1234 (2006) | |
| 2005 | ||
| 5 | John Sachs Beeckler, Warren J. Gross: FPGA Particle Graphics Hardware. FCCM 2005: 85-94 | |
| 4 | Shaoqiang Bi, Warren J. Gross, Wei Wang, Asim J. Al-Khalili, M. N. S. Swamy: An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction. IWSOC 2005: 396-399 | |
| 3 | Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak: Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders. VLSI Signal Processing 39(1-2): 93-111 (2005) | |
| 2004 | ||
| 2 | Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak: An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding. FCCM 2004: 310-311 | |
| 2003 | ||
| 1 | Emmanuel Boutillon, Warren J. Gross, P. Glenn Gulak: VLSI architectures for the MAP algorithm. IEEE Transactions on Communications 51(2): 175-185 (2003) | |
Colors in the list of coauthors
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