Daniel Große

	2012
52		Finn Haedicke, Daniel Große, Rolf Drechsler: A guiding coverage metric for formal verification. DATE 2012: 617-622
	2011
51		Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler: Simulation-based equivalence checking between SystemC models at different levels of abstraction. ACM Great Lakes Symposium on VLSI 2011: 223-228
50		Mohamed Bawadekji, Daniel Große, Rolf Drechsler: TLM protocol compliance checking at the Electronic System Level. DDECS 2011: 435-440
49		Marc Michael, Daniel Große, Rolf Drechsler: Analyzing dependability measures at the Electronic System Level. FDL 2011: 1-8
48		Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler: Debugging reversible circuits. Integration 44(1): 51-61 (2011)
	2010
47		Daniel Große, Rolf Drechsler: Quality-Driven SystemC Design Springer 2010
46		Hoang M. Le, Daniel Große, Rolf Drechsler: Towards analyzing functional coverage in SystemC TLM property checking. HLDVT 2010: 67-74
45		Daniel Große, Hoang M. Le, Rolf Drechsler: Proving transaction and system-level properties of untimed SystemC TLM designs. MEMOCODE 2010: 113-122
44		Hoang M. Le, Daniel Große, Rolf Drechsler: Automatic Fault Localization for SystemC TLM Designs. MTV 2010: 35-40
43		Ulrich Kühne, Daniel Große, Rolf Drechsler: Towards Fully Automatic Synthesis of Embedded Software. Embedded Systems Letters 2(3): 53-57 (2010)
	2009
42		Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler: Contradictory antecedent debugging in bounded model checking. ACM Great Lakes Symposium on VLSI 2009: 173-176
41		Ulrich Kühne, Daniel Große, Rolf Drechsler: Property analysis and design understanding. DATE 2009: 1246-1249
40		Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler: Debugging of Toffoli networks. DATE 2009: 1284-1289
39		Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler: SMT-based stimuli generation in the SystemC Verification library. FDL 2009: 1-6
38		André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler: WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping 2009: 11-17
37		Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler: Equivalence Checking of Reversible Circuits. ISMVL 2009: 324-330
36		Daniel Große, Hoang M. Le, Rolf Drechsler: Induction-Based Formal Verification of SystemC TLM Designs. MTV 2009: 101-106
35		Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler: Reversible Logic Synthesis with Output Permutation. VLSI Design 2009: 189-194
34		Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 703-715 (2009)
33		Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Synthesis of Elementary Quantum Gate Circuits. Multiple-Valued Logic and Soft Computing 15(4): 283-300 (2009)
	2008
32		Daniel Große: Quality-Driven Design and Verification Flow for Digital Systems. Ausgezeichnete Informatikdissertationen 2008: 121-130
31		Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große: Quantified Synthesis of Reversible Logic. DATE 2008: 1015-1020
30		Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler: Contradiction Analysis for Constraint-based Random Simulation. FDL 2008: 130-135
29		Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ISMVL 2008: 214-219
28		Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler: RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ISMVL 2008: 220-225
27		Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler: Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. ISVLSI 2008: 411-416
26		Ulrich Kühne, Daniel Große, Rolf Drechsler: Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow. MTV 2008: 88-93
25		Daniel Große, Ulrich Kühne, Rolf Drechsler: Analyzing Functional Coverage in Bounded Model Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1305-1314 (2008)
	2007
24		Daniel Große, Rüdiger Ebendt, Rolf Drechsler: Improvements for constraint solving in the systemc verification library. ACM Great Lakes Symposium on VLSI 2007: 493-496
23		Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler: Exact sat-based toffoli network synthesis. ACM Great Lakes Symposium on VLSI 2007: 96-101
22		Daniel Große, Ulrich Kühne, Rolf Drechsler: Estimating functional coverage in bounded model checking. DATE 2007: 1176-1181
21		Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler: Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques. FDL 2007: 146-151
20		Robert Wille, Daniel Große: Fast exact Toffoli network synthesis of reversible logic. ICCAD 2007: 60-64
19		Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler: Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. ISMVL 2007: 50
18		Ulrich Kühne, Daniel Große, Rolf Drechsler: Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. ISVLSI 2007: 165-170
17		Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler: SWORD: A SAT like prover using word level information. VLSI-SoC 2007: 88-93
	2006
16		Daniel Große, Ulrich Kühne, Rolf Drechsler: HW/SW co-verification of embedded systems using bounded model checking. ACM Great Lakes Symposium on VLSI 2006: 43-48
15		Görschwin Fey, Daniel Große, Rolf Drechsler: Avoiding false negatives in formal verification for protocol-driven blocks. DATE 2006: 1225-1226
	2005
14		Daniel Große, Rolf Drechsler: Acceleration of SAT-Based Iterative Property Checking. CHARME 2005: 349-353
13		Daniel Große, Ulrich Kühne, Rolf Drechsler: Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. GI Jahrestagung (1) 2005: 308-312
12		Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große: SyCE: An Integrated Environment for System Design in SystemC. IEEE International Workshop on Rapid System Prototyping 2005: 258-260
11		Daniel Große, Rolf Drechsler: CheckSyC: an efficient property checker for RTL SystemC designs. ISCAS (4) 2005: 4167-4170
10		Daniel Große, Ulrich Kühne, Rolf Drechsler: HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. MTV 2005: 133-137
	2004
9		Daniel Große, Rolf Drechsler: Checkers for SystemC designs. MEMOCODE 2004: 171-178
	2003
8		Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst: Efficient Automatic Visualization of SystemC Designs. FDL 2003: 646-658
7		Daniel Große, Rolf Drechsler: Formal verification of LTL formulas for SystemC designs. ISCAS (5) 2003: 245-248
6		Daniel Große, Görschwin Fey, Rolf Drechsler: Modeling Multi-Valued Circuits in SystemC. ISMVL 2003: 281-286
5		Daniel Große, Rolf Drechsler: Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC. it - Information Technology 45(4): 219-226 (2003)
	2002
4		Rolf Drechsler, Daniel Große: Reachability Analysis for Formal Verification of SystemC. DSD 2002: 337-340
3		Frank Schmiedle, Nicole Drechsler, Daniel Große, Rolf Drechsler: Heuristic Learning Based on Genetic Programming. Genetic Programming and Evolvable Machines 3(4): 363-388 (2002)
	2001
2		Nicole Drechsler, Frank Schmiedle, Daniel Große, Rolf Drechsler: Heuristic Learning Based on Genetic Programming. EuroGP 2001: 1-10
1		Frank Schmiedle, Daniel Große, Rolf Drechsler, Bernd Becker: Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics. Fuzzy Days 2001: 479-491

Coauthor Index

1	Mahsan Amoui	[19]
2	Gerhard Angst	[8]
3	Mohamed Bawadekji	[50]
4	Bernd Becker	[1]
5	Xiaobo Chen	[23]
6	Nicole Drechsler	[2] [3]
7	Rolf Drechsler	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52]
8	Gerhard W. Dueck	[23] [28] [29] [31] [33] [34] [35] [40] [48]
9	Rüdiger Ebendt	[24]
10	Stephan Eggersglüß	[17]
11	Görschwin Fey	[6] [12] [15] [17] [38]
12	Stefan Frehse	[40] [48]
13	Christian Genz	[12]
14	Markus Groß	[51]
15	Finn Haedicke	[39] [52]
16	Wolfgang Klingauf	[21]
17	Ulrich Kühne	[10] [13] [16] [18] [22] [25] [26] [38] [41] [42] [43] [51]
18	Hoang M. Le	[31] [36] [44] [45] [46]
19	Lothar Linhard	[8]
20	Marc Michael	[49]
21	D. Michael Miller	[37]
22	Hernan Peraza	[21]
23	Frank Schmiedle	[1] [2] [3]
24	Robert Siegmund	[30]
25	Mathias Soeken	[27]
26	André Sülflow	[38]
27	Lisa Teuber	[28]
28	Mitchell A. Thornton (Mitchell Aaron Thornton)	[19]
29	Robert Wille	[17] [20] [27] [28] [29] [30] [31] [33] [34] [35] [37] [39] [40] [42] [48]

Last update Thu May 31 18:55:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page