Gary Grise

	2010
6		Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise: Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC 2010: 724-733
	2007
5		Anis Uzzaman, Bibo Li, Thomas J. Snethen, Brion L. Keller, Gary Grise: Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation. ITC 2007: 1-10
4		Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland: An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs. VTS 2007: 173-178
	2006
3		Vikram Iyengar, Mark Johnson, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Phil Stevens, Mark Taylor, Frank Woytowich: Performance verification of high-performance ASICs using at-speed structural test. ACM Great Lakes Symposium on VLSI 2006: 247-252
2		Vikram Iyengar, Gary Grise, Mark Taylor: A flexible and scalable methodology for GHz-speed structural test. DAC 2006: 314-319
1		Vikram Iyengar, Toshihiko Yokota, Kazuhiro Yamada, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Mark Johnson, Dave Milton, Mark Taylor, Frank Woytowich: At-Speed Structural Test For High-Performance ASICs. ITC 2006: 1-10

Coauthor Index

1	Theo Anemikos	[1] [3]
2	Bob Bassett	[1] [3]
3	Krishna Chakravadhanula	[6]
4	Vivek Chickermane	[6]
5	Mike Degregorio	[1] [3] [4]
6	Rudy Farmer	[1] [3]
7	Andrew Ferko	[4]
8	Brian Foutz	[6]
9	Vikram Iyengar	[1] [2] [3] [4] [6]
10	Mark Johnson	[1] [3]
11	Brion L. Keller	[5] [6]
12	David E. Lackey	[4] [6]
13	Bibo Li	[5]
14	R. Malneedi	[6]
15	Dave Milton	[1]
16	Steven F. Oakland	[4]
17	Kenneth Pichamuthu	[4]
18	Thomas J. Snethen	[5] [6]
19	Phil Stevens	[3]
20	Mark Taylor	[1] [2] [3] [4]
21	Anis Uzzaman	[5]
22	Frank Woytowich	[1] [3] [4]
23	Kazuhiro Yamada	[1]
24	Toshihiko Yokota	[1]

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