 | 2012 |
| 33 |  | Maxwell Walton,
Omar Ahmed,
Gary William Grewal,
Shawki Areibi:
An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C.
VLSI Design 2012: (2012) |
| 2011 |
| 32 |  | Christian Fobel,
Gary Gréwal,
Deborah Stacey:
Using GPUs to accelerate FPGA wirelength estimate for use with complex search operators.
CCECE 2011: 1129-1134 |
| 31 |  | N. Girard,
William B. Gardner,
John D. Carter,
Gary Gréwal:
CellPilot: A Seamless Communication Solution for Hybrid Cell Clusters.
ICPP Workshops 2011: 259-268 |
| 30 |  | M. Xu,
Gary Gréwal,
Shawki Areibi:
StarPlace: A new analytic method for FPGA placement.
Integration 44(3): 192-204 (2011) |
| 2010 |
| 29 |  | Ed Armstrong,
Gary William Grewal,
Shawki Areibi,
Gerarda Darlington:
An investigation of parallel memetic algorithms for VLSI circuit partitioning on multi-core computers.
CCECE 2010: 1-6 |
| 28 |  | Maxwell Walton,
Gary Gréwal,
Gerarda Darlington:
Parallel FPGA-based implementation of scatter search.
GECCO 2010: 1075-1082 |
| 27 |  | Maxwell Walton,
Gary William Grewal,
Gerarda Darlington:
Hardware acceleration of Scatter Search.
HPCS 2010: 436-443 |
| 26 |  | John D. Carter,
William B. Gardner,
Gary Gréwal:
The pilot approach to cluster programming in C.
IPDPS Workshops 2010: 1-8 |
| 25 |  | John D. Carter,
William B. Gardner,
Gary Gréwal:
The pilot library for novice MPI programmers.
PPOPP 2010: 351-352 |
| 24 |  | Ming Xu,
Gary Gréwal:
A Graph-Based I/O Pad Pre-placement Technique for Use with Analytic FPGA Placement Methods.
VLSI Design 2010: 63-68 |
| 2009 |
| 23 |  | Ming Xu,
Gary Gréwal,
Shawki Areibi,
Charlie Obimbo,
Dilip K. Banerji:
Near-linear wirelength estimation for FPGA placement.
CCECE 2009: 1198-1203 |
| 22 |  | Shawki Areibi,
X. Bao,
Gary Gréwal,
Dilip K. Banerji,
Peng Du:
Meta-Heuristic Based Techniques for FPGA Placement: A Study.
I. J. Comput. Appl. 16(1): 13-33 (2009) |
| 21 |  | Christian Fobel,
Gary Gréwal,
Andrew Morton:
Hardware accelerated FPGA placement.
Microelectronics Journal 40(11): 1667-1671 (2009) |
| 2008 |
| 20 |  | Christian Fobel,
Gary Gréwal:
A parallel Steiner tree heuristic for macro cell routing.
ICCD 2008: 27-33 |
| 2007 |
| 19 |  | Gary Gréwal,
S. Coros,
Dilip K. Banerji,
Andrew Morton:
Assigning data to dual memory banks in DSPs with a genetic algorithm using a repair heuristic.
Appl. Intell. 26(1): 53-67 (2007) |
| 2006 |
| 18 |  | Gary Gréwal,
S. Coros,
Dilip K. Banerji,
Andrew Morton:
Comparing a Genetic Algorithm Penalty Function and Repair Heuristic in the DSP Application Domain.
Artificial Intelligence and Applications 2006: 31-39 |
| 17 |  | Shouvik Chowdhury,
Gary William Grewal,
Dilip K. Banerji:
Clustering Hanan Points to Reduce Vlsi Interconnect Routing Times.
CCECE 2006: 1223-1227 |
| 16 |  | Gary Gréwal,
S. Coros,
M. Ventresca:
A Memetic Algorithm for Performing Memory Assignment in Dual-Bank DSPs.
International Journal of Computational Intelligence and Applications 6(4): 473-497 (2006) |
| 2004 |
| 15 |  | Peng Du,
Gary William Grewal,
Shawki Areibi,
Dilip K. Banerji:
A Fast Hierarchical Approach to FPGA Placement.
ESA/VLSI 2004: 497-503 |
| 14 |  | Gary William Grewal,
Ming Xu,
Charlie Obimbo:
An Approximate Solution for Steiner Trees in Multicast Routing.
IC-AI 2004: 707-711 |
| 13 |  | Gary William Grewal,
Thomas Charles Wilson,
Ming Xu,
Dilip K. Banerji:
Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees.
VLSI Design 2004: 855-862 |
| 2003 |
| 12 |  | Gary William Grewal,
Mike O'Cleirigh,
Charlie Obimbo:
Hierarchical Genetic Algorithms Applied to Datapath Synthesis.
IC-AI 2003: 994-1002 |
| 11 |  | Gary Gréwal,
Mike O'Cleirigh,
Mark Wineberg:
An evolutionary approach to behavioural-level synthesis.
IEEE Congress on Evolutionary Computation (1) 2003: 264-272 |
| 10 |  | Gary William Grewal,
Thomas Charles Wilson:
Mapping Reference Code to Irregular DSPS within the Retargetable, Optimizing Compiler Cogen(T).
International Journal of Computational Intelligence and Applications 3(1): 45-64 (2003) |
| 9 |  | Gary Gréwal,
Tom Wilson,
Andrew Morton:
An EGA approach to the compile-time assignment of data to multiple memories in digital-signal processors.
SIGARCH Computer Architecture News 31(1): 49-59 (2003) |
| 2002 |
| 8 |  | Gary William Grewal,
Thomas Charles Wilson,
Christopher W. Nell:
An Enhanced Genetic Algorithm Approach to the Channel Assignment Problem in Mobile Cellular Networks.
Canadian Conference on AI 2002: 325-333 |
| 2001 |
| 7 |  | Gary William Grewal,
Thomas Charles Wilson:
Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T).
MICRO 2001: 192-202 |
| 6 |  | Gary William Grewal,
Thomas Charles Wilson:
An Enhanced Genetic Algorithm for Solving the High-Level Synthesis Problems of Scheduling, Allocation, and Binding.
International Journal of Computational Intelligence and Applications 1(1): 91-110 (2001) |
| 1997 |
| 5 |  | Thomas Charles Wilson,
Gary William Grewal:
Shake And Bake: A Method of Mapping Code to Irregular DSPs.
VLSI Design 1997: 506-508 |
| 4 |  | Gary William Grewal,
Thomas Charles Wilson:
An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design.
VLSI Design 1997: 51-56 |
| 1996 |
| 3 |  | Gary William Grewal:
A Global Mode Instruction Minimization Technique for Embedded DSPs.
Great Lakes Symposium on VLSI 1996: 18- |
| 1994 |
| 2 |  | Thomas Charles Wilson,
Gary William Grewal,
Shawn Henshall,
Dilip K. Banerji:
An ILP-based approach to code generation.
Code Generation for Embedded Processors 1994: 103-118 |
| 1 |  | Thomas Charles Wilson,
Gary William Grewal,
Dilip K. Banerji:
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis.
ICCD 1994: 581-586 |