 | 2011 |
|---|
| 7 |       | Marius Grannæs,
Magnus Jahre,
Lasse Natvig:
Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy.
ARCS 2011: 135-146 |
| 2010 |
|---|
| 6 | | Marius Grannæs,
Magnus Jahre,
Lasse Natvig:
Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching.
HiPEAC 2010: 247-261 |
| 5 | | Magnus Jahre,
Marius Grannæs,
Lasse Natvig:
DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems.
HiPEAC 2010: 292-306 |
| 2009 |
|---|
| 4 | | Magnus Jahre,
Marius Grannæs,
Lasse Natvig:
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures.
HPCC 2009: 622-629 |
| 2008 |
|---|
| 3 | | Marius Grannæs,
Magnus Jahre,
Lasse Natvig:
Low-cost open-page prefetch scheduling in chip multiprocessors.
ICCD 2008: 390-396 |
| 2006 |
|---|
| 2 | | Haakon Dybdahl,
Marius Grannæs,
Lasse Natvig:
Cache Write-Back Schemes for Embedded Destructive-Read DRAM.
ARCS 2006: 145-159 |
| 1 | | Haakon Dybdahl,
Per Gunnar Kjeldsberg,
Marius Grannæs,
Lasse Natvig:
Destructive-read in embedded DRAM, impact on power consumption.
J. Embedded Computing 2(2): 249-260 (2006) |
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