Matt Grange

Matthew Grange

	2011
7		Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa: Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. ICCAD 2011: 310-317
6		Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa, Axel Jantsch, Awet Yemane Weldezion: Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks. NOCS 2011: 57-64
5		Dinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, Axel Jantsch: 3-D integration and the limits of silicon computation. VLSI-SoC 2011: 343-348
	2010
4		Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen: On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. DATE 2010: 1325-1328
	2009
3		Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen: Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. 3DIC 2009: 1-7
2		Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen, Li-Rong Zheng: Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. 3DIC 2009: 1-8
1		Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen: Scalability of network-on-chip communication architecture for 3-D meshes. NOCS 2009: 114-123

Coauthor Index

1	Axel Jantsch	[1] [3] [5] [6] [7]
2	Zhonghai Lu	[1] [3]
3	Dinesh Pamunuwa	[1] [2] [3] [4] [5] [6] [7]
4	Dave Shippen	[3]
5	Hannu Tenhunen	[1] [2] [4]
6	Roshan Weerasekera	[1] [2] [3] [4] [5] [6] [7]
7	Awet Yemane Weldezion	[1] [3] [6]
8	Li-Rong Zheng	[2]

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