Helmut E. Graeb

Helmut Gräb

	2011
36		Michael Eick, Martin Strasser, Kun Lu, Ulf Schlichtmann, Helmut E. Graeb: Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 180-193 (2011)
	2010
35		Michael Pehl, Michael Zwerger, Helmut E. Graeb: Sizing analog circuits using an SQP and Branch and Bound based approach. ICECS 2010: 37-40
34		Michael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann: Automatic generation of hierarchical placement rules for analog integrated circuits. ISPD 2010: 47-54
	2009
33		Helmut Gräb, Florin Balasa, R. Castro-López, Yu-Wei Chang, Francisco V. Fernández, Mark Po-Hung Lin, Martin Strasser: Analog layout synthesis - Recent advances in topological approaches. DATE 2009: 274-279
32		Daniel Mueller-Gritschneder, Helmut E. Graeb, Ulf Schlichtmann: A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems. SIAM Journal on Optimization 20(2): 915-934 (2009)
	2008
31		David Binkley, Helmut E. Graeb, Georges G. E. Gielen, Jaijeet S. Roychowdhury: From Transistor to PLL - Analogue Design and EDA Methods. DATE 2008
30		Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann: Sizing Rules for Bipolar Analog Circuit Design. DATE 2008: 140-145
29		Martin Strasser, Michael Eick, Helmut Gräb, Ulf Schlichtmann, Frank M. Johannes: Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions. ICCAD 2008: 306-313
28		Michael Pehl, Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann: A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters. ICCD 2008: 188-193
27		Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann: The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2209-2222 (2008)
	2007
26		Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann: Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming. DATE 2007: 75-80
25		Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann: Pareto-Front Computation and Automatic Sizing of CPPLLs. ISQED 2007: 481-486
24		Guido Stehr, Helmut E. Graeb, Kurt Antreich: Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1733-1748 (2007)
	2006
23		Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann: A CPPLL hierarchical optimization methodology considering jitter, power and locking time. DAC 2006: 19-24
22		Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann: Fast evaluation of analog circuit structures by polytopal approximations. ISCAS 2006
	2005
21		Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann: Deterministic approaches to analog performance space exploration (PSE). DAC 2005: 869-874
20		Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann: Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen. GI Jahrestagung (1) 2005: 334-338
	2004
19		Guido Stehr, Helmut E. Graeb, Kurt Antreich: Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing. ICCAD 2004: 847-854
	2003
18		Guido Stehr, Helmut E. Graeb, Kurt Antreich: Performance trade-off analysis of analog circuits by normal-boundary intersection. DAC 2003: 958-963
17		Guido Stehr, Michael Pronath, Frank Schenkel, Helmut E. Graeb, Kurt Antreich: Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification. ICCAD 2003: 241-246
	2002
16		Robert Schwencker, Frank Schenkel, Michael Pronath, Helmut E. Graeb: Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets. DATE 2002: 581-585
15		Michael Pronath, Helmut E. Graeb, Kurt Antreich: A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits. DATE 2002: 78-83
	2001
14		Frank Schenkel, Michael Pronath, Stephan Zizala, Robert Schwencker, Helmut E. Graeb, Kurt Antreich: Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search. DAC 2001: 858-863
13		Helmut E. Graeb, Stephan Zizala, Josef Eckmueller, Kurt Antreich: The Sizing Rules Method for Analog Integrated Circuit Design. ICCAD 2001: 343-349
	2000
12		Robert Schwencker, Frank Schenkel, Helmut E. Graeb, Kurt Antreich: The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits. DATE 2000: 42-47
11		Michael Pronath, Volker Gloeckel, Helmut E. Graeb: A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits. ICCAD 2000: 557-561
	1999
10		Robert Schwencker, Josef Eckmueller, Helmut E. Graeb, Kurt Antreich: Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints. DATE 1999: 323-327
9		Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich: Analog testing by characteristic observation inference. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1353-1368 (1999)
	1998
8		Josef Eckmueller, Martin Groepl, Helmut E. Graeb: Hierarchical Characterization of Analog Integrated CMOS Circuits. DATE 1998: 636-643
7		Walter M. Lindermeir, Thomas J. Vogels, Helmut E. Graeb: Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults. DATE 1998: 822-827
	1995
6		Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich: Design based analog testing by Characteristic Observation Inference. ICCAD 1995: 620-626
	1994
5		Wolfgang T. Eisenmann, Helmut E. Graeb: Fast transient power and noise estimation for VLSI circuits. ICCAD 1994: 252-257
4		Kurt Antreich, Helmut E. Graeb, Claudia U. Wieser: Circuit analysis and optimization driven by worst-case distances. IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 57-71 (1994)
	1993
3		Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich: Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances. DAC 1993: 142-147
	1992
2		Helmut E. Graeb, Reiner E. Lederle: Circuit yield optimization by analyzing performance statistics. Microprocessing and Microprogramming 35(1-5): 697-703 (1992)
	1991
1		Kurt Antreich, Helmut E. Graeb: Circuit Optimization Driven by Worst-Case Distances. ICCAD 1991: 166-169

Coauthor Index

1	Kurt Antreich	[1] [3] [4] [6] [9] [10] [12] [13] [14] [15] [17] [18] [19] [24]
2	Florin Balasa	[33]
3	David Binkley	[31]
4	R. Castro-López (Rafael Castro-López)	[33]
5	Yu-Wei Chang	[33]
6	Josef Eckmueller	[8] [10] [13]
7	Michael Eick	[29] [34] [36]
8	Wolfgang T. Eisenmann	[5]
9	Francisco V. Fernández (Francisco Vidal Fernández Fernández)	[33]
10	Georges G. E. Gielen	[31]
11	Volker Gloeckel (Volker Glöckel)	[11]
12	Martin Groepl	[8]
13	Frank M. Johannes	[29]
14	Reiner E. Lederle	[2]
15	Mark Po-Hung Lin	[33]
16	Walter M. Lindermeir	[6] [7] [9]
17	Kun Lu	[36]
18	Tobias Massier	[27] [28] [30]
19	Daniel Mueller	[20] [21] [22] [23] [25] [26]
20	Daniel Mueller-Gritschneder	[32]
21	Michael Pehl	[28] [35]
22	Michael Pronath	[11] [14] [15] [16] [17]
23	Jaijeet S. Roychowdhury	[31]
24	Frank Schenkel	[12] [14] [16] [17]
25	Ulf Schlichtmann	[20] [21] [22] [23] [25] [26] [27] [28] [29] [30] [32] [34] [36]
26	Robert Schwencker	[10] [12] [14] [16]
27	Guido Stehr	[17] [18] [19] [20] [21] [22] [24]
28	Martin Strasser	[29] [33] [34] [36]
29	Thomas J. Vogels	[7]
30	Claudia U. Wieser	[3] [4]
31	Stephan Zizala	[13] [14]
32	Jun Zou	[23] [25]
33	Michael Zwerger	[35]

Colors in the list of coauthors

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