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Ramaswamy Govindarajan
List of publications from the DBLP Bibliography Server - FAQ
| 2012 | ||
|---|---|---|
| 100 | T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar: On-chip memory architecture exploration framework for DSP processor-based embedded system on chip. ACM Trans. Embedded Comput. Syst. 11(1): 5 (2012) | |
| 2011 | ||
| 99 | Rupesh Nasre, Ramaswamy Govindarajan: Prioritizing constraint evaluation for efficient points-to analysis. CGO 2011: 267-276 | |
| 98 | R. Manikantan, Kaushik Rajan, R. Govindarajan: NUcache: An efficient multicore cache organization based on Next-Use distance. HPCA 2011: 243-253 | |
| 97 | R. Manikantan, R. Govindarajan, Kaushik Rajan: Extended histories: improving regularity and performance in correlation prefetchers. HiPEAC 2011: 67-76 | |
| 96 | Sandya S. Mannarswamy, Ramaswamy Govindarajan: Variable Granularity Access Tracking Scheme for Improving the Performance of Software Transactional Memory. IPDPS 2011: 455-466 | |
| 95 | Nagendra Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale: Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs. PACT 2011: 189-190 | |
| 94 | Sandya Mannarswamy, Ramaswamy Govindarajan: Making STMs Cache Friendly with Compiler Transformations. PACT 2011: 232-242 | |
| 93 | Ashwin Prasad, Jayvant Anantpur, R. Govindarajan: Automatic compilation of MATLAB programs for synergistic execution on heterogeneous processors. PLDI 2011: 152-163 | |
| 92 | Mrugesh R. Gajjar, T. V. Sreenivas, R. Govindarajan: Fast computation of Gaussian likelihoods using low-rank matrix approximations. SiPS 2011: 322-327 | |
| 2010 | ||
| 91 | R. Govindarajan, David A. Padua, Mary W. Hall: Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2010, Bangalore, India, January 9-14, 2010 ACM 2010 | |
| 90 | Sandya Mannarswamy, R. Govindarajan: Handling Conflicts with Compiler's Help in Software Transactional Memory Systems. ICPP 2010: 482-491 | |
| 89 | Sandya S. Mannarswamy, Ramaswamy Govindarajan: Analyzing cache performance bottlenecks of STM applications and addressing them with compiler's help. PACT 2010: 547-548 | |
| 88 | R. Manikantan, Kaushik Rajan, R. Govindarajan: NUcache: a multicore cache organization based on next-use distance. PACT 2010: 569-570 | |
| 87 | Rupesh Nasre, Ramaswamy Govindarajan: Points-to Analysis as a System of Linear Equations. SAS 2010: 422-438 | |
| 2009 | ||
| 86 | Rupesh Nasre, Kaushik Rajan, Ramaswamy Govindarajan, Uday P. Khedker: Scalable Context-Sensitive Points-to Analysis Using Multi-dimensional Bloom Filters. APLAS 2009: 47-62 | |
| 85 | Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil: Software Pipelined Execution of Stream Programs on GPUs. CGO 2009: 200-209 | |
| 84 | Girish B. C., Ramaswamy Govindarajan: Reducing Buffer Requirements in Core Routers Using Dynamic Buffering. ICCCN 2009: 1-6 | |
| 83 | Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil: Synergistic execution of stream programs on multicores with accelerators. LCTES 2009: 99-108 | |
| 82 | Sandya S. Mannarswamy, Ramaswamy Govindarajan, Rishi Surendran: Region Based Structure Layout Optimization by Selective Data Copying. PACT 2009: 338-347 | |
| 81 | Kaushik Rajan, Ramaswamy Govindarajan: A Novel Cache Architecture and Placement Framework for Packet Forwarding Engines. IEEE Trans. Computers 58(8): 1009-1025 (2009) | |
| 2008 | ||
| 80 | Aditya V. Thakur, R. Govindarajan: Comprehensive path-sensitive data-flow analysis. CGO 2008: 55-63 | |
| 79 | Girish Chandramohan, Ramaswamy Govindarajan: Improving Performance of Digest Caches in Network Processors. HiPC 2008: 6-17 | |
| 78 | R. Manikantan, R. Govindarajan: Focused prefetching: performance oriented prefetching based on commit stalls. ICS 2008: 339-348 | |
| 77 | Mrugesh R. Gajjar, R. Govindarajan, T. V. Sreenivas: Online unsupervised pattern discovery in speech using parallelization. INTERSPEECH 2008: 2458-2461 | |
| 76 | Sudhakar Surendran, Rubin A. Parekhji, R. Govindarajan: A systematic approach to synthesis of verification test-suites for modular SoC designs. SoCC 2008: 91-96 | |
| 75 | T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan: Memory Architecture Exploration Framework for Cache Based Embedded SOC. VLSI Design 2008: 553-559 | |
| 74 | V. Santhosh Kumar, R. Nanjundiah, Matthew J. Thazhuthaveetil, R. Govindarajan: Impact of message compression on the scalability of an atmospheric modeling application on clusters. Parallel Computing 34(1): 1-16 (2008) | |
| 2007 | ||
| 73 | T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan: MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip. ASP-DAC 2007: 492-497 | |
| 72 | Santosh G. Nagarakatte, R. Govindarajan: Register Allocation and Optimal Spill Code Scheduling in Software Pipelined Loops Using 0-1 Integer Linear Programming Formulation. CC 2007: 126-140 | |
| 71 | K. Shyam, R. Govindarajan: An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures. CC 2007: 32-47 | |
| 70 | K. Shyam, R. Govindarajan: Compiler-Directed Dynamic Voltage Scaling Using Program Phases. HiPC 2007: 233-244 | |
| 69 | S. Govind, R. Govindarajan, Joy Kuri: Packet Reordering in Network Processors. IPDPS 2007: 1-10 | |
| 68 | Kaushik Rajan, Ramaswamy Govindarajan: Emulating Optimal Replacement with a Shepherd Cache. MICRO 2007: 445-454 | |
| 67 | Kaushik Rajan, Ramaswamy Govindarajan, Bharadwaj Amrutur: Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses. PACT 2007: 422 | |
| 66 | Rajesh Vivekanandham, R. Govindarajan: A Scalable Low Power Store Queue for Large InstructionWindow Processors. PACT 2007: 430 | |
| 65 | Girish B. C., R. Govindarajan: A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor. QEST 2007: 19-30 | |
| 64 | T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan: MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip. VLSI Design 2007: 527-533 | |
| 63 | Rajani Pai, R. Govindarajan: FEADS: A Framework for Exploring the Application Design Space on Network Processors. International Journal of Parallel Programming 35(1): 1-31 (2007) | |
| 62 | Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao: Single-dimension software pipelining for multidimensional loops. TACO 4(1): (2007) | |
| 2006 | ||
| 61 | Rajesh Vivekanandham, Bharadwaj S. Amrutur, R. Govindarajan: A scalable low power issue queue for large instruction window processors. ICS 2006: 167-176 | |
| 60 | V. Santhosh Kumar, Matthew J. Thazhuthaveetil, R. Govindarajan: Exploiting programmable network interfaces for parallel query execution in workstation clusters. IPDPS 2006 | |
| 59 | Kaushik Rajan, Ramaswamy Govindarajan: Two-level mapping based cache index selection for packet forwarding engines. PACT 2006: 212-221 | |
| 58 | Subash G. Chandar, Mahesh Mehendale, R. Govindarajan: Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. VLSI Signal Processing 44(3): 245-267 (2006) | |
| 2005 | ||
| 57 | V. Santhosh Kumar, Matthew J. Thazhuthaveetil, R. Govindarajan: Offloading Bloom Filter Operations to Network Processor for Parallel Query Processing in Cluster of Workstations. HiPC 2005: 170-179 | |
| 56 | Kaushik Rajan, Ramaswamy Govindarajan: A heterogeneously segmented cache architecture for a packet forwarding engine. ICS 2005: 71-80 | |
| 55 | S. Govind, R. Govindarajan: Performance Modeling and Architecture Exploration of Network Processors. QEST 2005: 189-198 | |
| 54 | Hongbo Yang, Ramaswamy Govindarajan, Guang R. Gao, Ziang Hu: Improving power efficiency with compiler-assisted cache replacement. J. Embedded Computing 1(4): 487-499 (2005) | |
| 2004 | ||
| 53 | Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao: Single-Dimension Software Pipelining for Multi-Dimensional Loops. CGO 2004: 163-174 | |
| 52 | Hongbo Rong, Alban Douillet, Ramaswamy Govindarajan, Guang R. Gao: Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops. CGO 2004: 175-188 | |
| 51 | N. P. Manoj, K. V. Manjunath, R. Govindarajan: CAS-DSM: A Compiler Assisted Software Distributed Shared Memory. International Journal of Parallel Programming 32(2): 77-122 (2004) | |
| 50 | Manjunath Kudlur, R. Govindarajan: Performance analysis of methods that overcome false sharing effects in software DSMs. J. Parallel Distrib. Comput. 64(8): 887-907 (2004) | |
| 2003 | ||
| 49 | A. Radhika Sarma, R. Govindarajan: An Efficient Web Cache Replacement Policy. HiPC 2003: 12-22 | |
| 48 | Guang R. Gao, Kevin B. Theobald, Ramaswamy Govindarajan, Clement Leung, Ziang Hu, Haiping Wu, Jizhu Lu, Juan del Cuvillo, Adeline Jacquet, Vincent Janot, Thomas L. Sterling: Programming Models and System Software for Future High-End Computing Systems: Work-in-Progress. IPDPS 2003: 206 | |
| 47 | Adeline Jacquet, Vincent Janot, Clement Leung, Guang R. Gao, Ramaswamy Govindarajan, Thomas L. Sterling: An Executable Analytical Performance Evaluation Approach for Early Performance Prediction. IPDPS 2003: 268 | |
| 46 | R. Achutharaman, R. Govindarajan, G. Hariprakash, Amos Omondi: Exploiting Java-ILP on a Simultaneous Multi-Trace Instruction Issue (SMTI) Processor. IPDPS 2003: 76 | |
| 45 | Hongbo Yang, Ramaswamy Govindarajan, Guang R. Gao, Ziang Hu: Compiler-Assisted Cache Replacement: Problem Formulation and Performance Evaluation. LCPC 2003: 77-92 | |
| 44 | V. V. N. S. Sarvani, R. Govindarajan: Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment. SCOPES 2003: 270-284 | |
| 43 | T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravi Kumar: Optimal Code and Data Layout in Embedded Systems. VLSI Design 2003: 573-578 | |
| 42 | Ramaswamy Govindarajan, Hongbo Yang, José Nelson Amaral, Chihong Zhang, Guang R. Gao: Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures. IEEE Trans. Computers 52(1): 4-20 (2003) | |
| 2002 | ||
| 41 | R. Vinodh Kumar, B. Lakshmi Narayanan, R. Govindarajan: Dynamic Path Profile Aided Recompilation in a JAVA Just-In-Time Compiler. HiPC 2002: 495-505 | |
| 40 | Hongbo Yang, Ramaswamy Govindarajan, Guang R. Gao, Kevin B. Theobald: Power-Performance Trade-Offs for Energy-Efficient Architectures: A Quantitative Study. ICCD 2002: 174-179 | |
| 39 | Ramaswamy Govindarajan: Instruction Scheduling. The Compiler Design Handbook 2002: 631-688 | |
| 38 | R. Govindarajan, Erik R. Altman, Guang R. Gao: A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors. Design Autom. for Emb. Sys. 6(3): 243-275 (2002) | |
| 37 | Ramaswamy Govindarajan, Guang R. Gao, Palash Desai: Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks. VLSI Signal Processing 31(3): 207-229 (2002) | |
| 2001 | ||
| 36 | K. V. Manjunath, R. Govindarajan: Hidden Costs in Avoiding False Sharing in Software DSMs. HiPC 2001: 294-306 | |
| 35 | Subash G. Chandar, Mahesh Mehendale, R. Govindarajan: Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding. ICCAD 2001: 631-634 | |
| 34 | Ramaswamy Govindarajan, Hongbo Yang, Chihong Zhang, José Nelson Amaral, Guang R. Gao: Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs. IPDPS 2001: 26 | |
| 33 | Ramaswamy Govindarajan, Anand Sivasubramaniam: Guest Editors' Introduction: Special Issue on Cluster and Network-Based Computing. J. Parallel Distrib. Comput. 61(11): 1507-1511 (2001) | |
| 2000 | ||
| 32 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao: A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors. ASAP 2000: 329-338 | |
| 31 | Ramaswamy Govindarajan, N. S. S. Narasimha Rao, Erik R. Altman, Guang R. Gao: Enhanced Co-Scheduling: A Software Pipelining Method Using Modulo-Scheduled Pipeline Theory. International Journal of Parallel Programming 28(1): 1-46 (2000) | |
| 30 | N. Sreraman, R. Govindarajan: A Vectorizing Compiler for Multimedia Extensions. International Journal of Parallel Programming 28(4): 363-400 (2000) | |
| 1999 | ||
| 29 | Chihong Zhang, Ramaswamy Govindarajan, Sean Ryan, Guang R. Gao: Efficient State-Diagram Construction Methods for Software Pipelining. CC 1999: 153-167 | |
| 28 | V. Janaki Ramanan, Ramaswamy Govindarajan: Resource Usage Modelling for Software Pipelining. HiPC 1999: 111-119 | |
| 27 | Madhavi Gopal Valluri, R. Govindarajan: Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors. IEEE PACT 1999: 78-83 | |
| 26 | V. Janaki Ramanan, Ramaswamy Govindarajan: Resource usage models for instruction scheduling: two new models and a classification. International Conference on Supercomputing 1999: 417-424 | |
| 25 | Ramaswamy Govindarajan, Chihong Zhang, Guang R. Gao: Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors. LCPC 1999: 70-84 | |
| 1998 | ||
| 24 | Ramaswamy Govindarajan, N. S. S. Narasimha Rao, Erik R. Altman, Guang R. Gao: An Enhanced Co-Scheduling Method Using Reduced MS-State Diagrams. IPPS/SPDP 1998: 168-175 | |
| 23 | Amod K. Dani, V. Janaki Ramanan, Ramaswamy Govindarajan: Register-Sensitive Software Pipelining. IPPS/SPDP 1998: 194-198 | |
| 22 | Erik R. Altman, Ramaswamy Govindarajan, Guang R. Gao: A Unified Framework for Instruction Scheduling and Mapping for Function Units with Structural Hazards. J. Parallel Distrib. Comput. 49(2): 259-293 (1998) | |
| 1997 | ||
| 21 | S. Ramesh, R. Lakshmi, R. Govindarajan: Distributed Shared Memory on IBM SP2. ICPADS 1997: 338-345 | |
| 20 | Rad Silvera, Jian Wang, Ramaswamy Govindarajan, Guang R. Gao: A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors. IEEE PACT 1997: 78-89 | |
| 1996 | ||
| 19 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao: Co-Scheduling Hardware and Software Pipelines. HPCA 1996: 52-61 | |
| 18 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao: A Framework for Resource-Constrained Rate-Optimal Software Pipelining. IEEE Trans. Parallel Distrib. Syst. 7(11): 1133-1149 (1996) | |
| 1995 | ||
| 17 | Ramaswamy Govindarajan, Shashank S. Nemawarkar, Phillip LeNir: Design and Performance Evaluation of a Multithreaded Architecture. HPCA 1995: 298-307 | |
| 16 | Erik R. Altman, Guang R. Gao, Ramaswamy Govindarajan: An Experimental Study of an ILP-based Exact Solution Method for Software Pipelining. LCPC 1995: 16-30 | |
| 15 | Erik R. Altman, Ramaswamy Govindarajan, Guang R. Gao: Scheduling and Mapping: Software Pipelining in the Presence of Structural Hazards. PLDI 1995: 139-150 | |
| 14 | Ramaswamy Govindarajan, Guang R. Gao: Rate-optimal schedule for multi-rate DSP computations. VLSI Signal Processing 9(3): 211-232 (1995) | |
| 1994 | ||
| 13 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao: A Framework for Resource-Constrained Rate-Optimal Software Pipelining. CONPAR 1994: 640-651 | |
| 12 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao: Minimizing register requirements under resource-constrained rate-optimal software pipelining. MICRO 1994: 85-94 | |
| 11 | Shashank S. Nemawarkar, Ramaswamy Govindarajan, Guang R. Gao, Vinod K. Agarwal: Performance of Interconnection Network in Multithreaded Architectures. PARLE 1994: 823-826 | |
| 1993 | ||
| 10 | Shashank S. Nemawarkar, Ramaswamy Govindarajan, Guang R. Gao, Vinod K. Agarwal: Analysis of Multithreaded Multiprocessors with Distributed Shared Memory. SPDP 1993: 114-121 | |
| 9 | R. Govindarajan: Exception Handlers in Functional Programming Languages. IEEE Trans. Software Eng. 19(8): 826-834 (1993) | |
| 1992 | ||
| 8 | Ramaswamy Govindarajan, Shashank S. Nemawarkar: A Large Context Multithreaded Architecture. CONPAR 1992: 423-428 | |
| 7 | Shashank S. Nemawarkar, Ramaswamy Govindarajan, Guang R. Gao, Vinod K. Agarwal: Performance Evaluation of Latency Tolerant Architectures. ICCI 1992: 183-186 | |
| 6 | Philip LeNir, Ramaswamy Govindarajan, Shashank S. Nemawarkar: Exploiting instruction-level parallelism: the multithreaded approach. MICRO 1992: 189-192 | |
| 5 | Ramaswamy Govindarajan, Shashank S. Nemawarkar: SMALL: A Scalable Multithreaded Architecture to Exploit Large Localiy. SPDP 1992: 32-39 | |
| 4 | R. Govindarajan, Sheng Yu, V. S. Lakshmanan: Attempting guards in parallel: A data flow approach to execute generalized guarded commands. International Journal of Parallel Programming 21(4): 225-268 (1992) | |
| 1991 | ||
| 3 | R. Govindarajan, Sheng Yu: Data Flow Implementation of Generalized Guarded Commands. PARLE (1) 1991: 372-389 | |
| 1990 | ||
| 2 | R. Govindarajan, Lalit M. Patnaik: Lenient Execution and Concurrent Execution of Re-Entrant Routines: Efficient Implementation in Data Flow Systems. Comput. J. 33(2): 185-187 (1990) | |
| 1986 | ||
| 1 | Lalit M. Patnaik, R. Govindarajan, N. S. Ramadoss: Design and Performance Evaluation of EXMAN: An EXtended MANchester Data Flow Computer. IEEE Trans. Computers 35(3): 229-244 (1986) | |
Colors in the list of coauthors
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