 | 2011 |
| 19 |  | Ryota Shioya,
Daewung Kim,
Kazuo Horio,
Masahiro Goshima,
Shuichi Sakai:
Low-Overhead Architecture for Security Tag.
IEICE Transactions 94-D(1): 69-78 (2011) |
| 2010 |
| 18 |  | Ryota Shioya,
Kazuo Horio,
Masahiro Goshima,
Shuichi Sakai:
Register Cache System Not for Latency Reduction Purpose.
MICRO 2010: 301-312 |
| 2009 |
| 17 |  | Ryota Shioya,
Daewung Kim,
Kazuo Horio,
Masahiro Goshima,
Shuichi Sakai:
Low-Overhead Architecture for Security Tag.
PRDC 2009: 135-142 |
| 16 |  | Kunbo Li,
Ryota Shioya,
Masahiro Goshima,
Shuichi Sakai:
String-Wise Information Flow Tracking against Script Injection Attacks.
PRDC 2009: 169-176 |
| 2008 |
| 15 |  | Shinobu Miwa,
Hironori Ichibayashi,
Hidetsugu Irie,
Masahiro Goshima,
Hironori Nakajo,
Shinji Tomita:
Low-Complexity Bypass Network Using Small RAM.
CDES 2008: 153-159 |
| 14 |  | Shuichi Sakai,
Masahiro Goshima,
Hidetsugu Irie:
Ultra Dependable Processor.
IEICE Transactions 91-C(9): 1386-1393 (2008) |
| 2007 |
| 13 |  | Luong Dinh Hung,
Hidetsugu Irie,
Masahiro Goshima,
Shuichi Sakai:
Utilization of SECDED for soft error and variation-induced defect tolerance in caches.
DATE 2007: 1134-1139 |
| 12 |  | Hidetsugu Irie,
Ken Sugimoto,
Masahiro Goshima,
Shuichi Sakai:
Preventing timing errors on register writes: mechanisms of detections and recoveries.
SIGARCH Computer Architecture News 35(5): 25-31 (2007) |
| 2006 |
| 11 |  | Satoshi Katsunuma,
Hiroyuki Kurita,
Ryota Shioya,
Kazuto Shimizu,
Hidetsugu Irie,
Masahiro Goshima,
Shuichi Sakai:
Base Address Recognition with Data Flow Tracking for Injection Attack Detection.
PRDC 2006: 165-172 |
| 10 |  | Luong Dinh Hung,
Masahiro Goshima,
Shuichi Sakai:
SEVA: A Soft-Error- and Variation-Aware Cache Architecture.
PRDC 2006: 47-54 |
| 2005 |
| 9 |  | Luong Dinh Hung,
Masahiro Goshima,
Shuichi Sakai:
Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag.
ICCD 2005: 342-350 |
| 2004 |
| 8 |  | Motohiro Takayama,
Yuki Shinomoto,
Masahiro Goshima,
Shin-ichiro Mori,
Yasuhiko Nakashima,
Shinji Tomita:
Implementation of Cell-Projection Parallel Volume Rendering with Dynamic Load Balancing.
PDPTA 2004: 373-382 |
| 2001 |
| 7 |  | Masahiro Goshima,
Kengo Nishino,
Toshiaki Kitamura,
Yasuhiko Nakashima,
Shinji Tomita,
Shin-ichiro Mori:
A high-speed dynamic instruction scheduling scheme for superscalar processors.
MICRO 2001: 225-236 |
| 1999 |
| 6 |  | Atsushi Kubota,
Shogo Tatsumi,
Toshihiko Tanaka,
Masahiro Goshima,
Shin-ichiro Mori,
Hiroshi Nakashima,
Shinji Tomita:
A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR.
International Journal of Parallel Programming 27(2): 97-109 (1999) |
| 1998 |
| 5 |  | Shin-ya Goto,
Atsushi Kubota,
Toshihiko Tanaka,
Masahiro Goshima,
Shin-ichiro Mori,
Hiroshi Nakashima,
Shinji Tomita:
Optimized Code Generation for Heterogeneous Computing Environment using Parallelizing Compiler TINPAR.
IEEE PACT 1998: 426-433 |
| 1997 |
| 4 |  | Kazuhiko Ohno,
Masahiko Ikawa,
Masahiro Goshima,
Shin-ichiro Mori,
Hiroshi Nakashima,
Shinji Tomita:
Efficient Goal Scheduling in Concurrent Logic Language using Type-Based Dependency Analysis.
ASIAN 1997: 268-282 |
| 3 |  | Atsushi Kubota,
Shogo Tatsumi,
Toshihiko Tanaka,
Masahiro Goshima,
Shin-ichiro Mori,
Hiroshi Nakashima,
Shinji Tomita:
A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR.
ISHPC 1997: 195-204 |
| 2 |  | Kazuhiko Ohno,
Masahiko Ikawa,
Shin-ichiro Mori,
Hiroshi Nakashima,
Shinji Tomita,
Masahiro Goshima:
Improvement of message communication in concurrent logic language.
PASCO 1997: 156-164 |
| 1993 |
| 1 |  | Shin-ichiro Mori,
Hideki Saito,
Masahiro Goshima,
Mamoru Yanagihara,
Takashi Tanaka,
David Fraser,
Kazuki Joe,
Hiroyuki Nitta,
Shinji Tomita:
A distributed shared memory multiprocessor ASURA: memory and cache architecture.
SC 1993: 740-749 |