 | 2012 |
| 50 |  | Marisha Rawlins,
Ann Gordon-Ross:
An application classification guided cache tuning heuristic for multi-core architectures.
ASP-DAC 2012: 23-28 |
| 49 |  | Arslan Munir,
Ann Gordon-Ross,
Susan Lysecky,
Roman L. Lysecky:
Online algorithms for wireless sensor networks dynamic optimization.
CCNC 2012: 180-187 |
| 48 |  | Wei Zang,
Ann Gordon-Ross:
A single-pass cache simulation methodology for two-level unified caches.
ISPASS 2012: 168-177 |
| 47 |  | Arslan Munir,
Ann Gordon-Ross:
An MDP-Based Dynamic Optimization Methodology for Wireless Sensor Networks.
IEEE Trans. Parallel Distrib. Syst. 23(4): 616-625 (2012) |
| 46 |  | Arslan Munir,
Sanjay Ranka,
Ann Gordon-Ross:
High-Performance Energy-Efficient Multicore Embedded Computing.
IEEE Trans. Parallel Distrib. Syst. 23(4): 684-700 (2012) |
| 2011 |
| 45 |  | Abelardo Jara-Berrocal,
Ann Gordon-Ross:
An integrated development toolset and implementation methodology for partially reconfigurable system-on-chips.
ASAP 2011: 219-222 |
| 44 |  | Marisha Rawlins,
Ann Gordon-Ross:
On the interplay of loop caching, code compression, and cache configuration.
ASP-DAC 2011: 243-248 |
| 43 |  | Wei Zang,
Ann Gordon-Ross:
T-SPaCS - A two-level single-pass cache simulation methodology.
ASP-DAC 2011: 419-424 |
| 42 |  | Rohit Kumar,
Ann Gordon-Ross:
Formulation-level design space exploration for partially reconfigurable FPGAs.
FPT 2011: 1-6 |
| 41 |  | Abelardo Jara-Berrocal,
Ann Gordon-Ross:
Hardware module reuse and runtime assembly for dynamic management of reconfigurable resources.
FPT 2011: 1-6 |
| 40 |  | Shaon Yousuf,
Adam Jacobs,
Ann Gordon-Ross:
Partially reconfigurable system-on-chips for adaptive fault tolerance.
FPT 2011: 1-8 |
| 39 |  | Arslan Munir,
Ann Gordon-Ross:
Markov Modeling of Fault-Tolerant Wireless Sensor Networks.
ICCCN 2011: 1-6 |
| 38 |  | Arslan Munir,
Ann Gordon-Ross,
Sanjay Ranka:
A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems.
ICCD 2011: 198-205 |
| 37 |  | Marisha Rawlins,
Ann Gordon-Ross:
CPACT - The conditional parameter adjustment cache tuner for dual-core architectures.
ICCD 2011: 396-403 |
| 36 |  | Saleh Abdel-Hafeez,
Ann Gordon-Ross:
A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic.
IEEE Trans. VLSI Syst. 19(6): 1023-1033 (2011) |
| 2010 |
| 35 |  | Marisha Rawlins,
Ann Gordon-Ross:
Lightweight runtime control flow analysis for adaptive loop caching.
ACM Great Lakes Symposium on VLSI 2010: 239-244 |
| 34 |  | Abelardo Jara-Berrocal,
Ann Gordon-Ross:
VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems.
DATE 2010: 837-842 |
| 33 |  | Ann Gordon-Ross,
Abelardo Jara-Berrocal:
VAPRES: A Customizable and Flexible Base Architecture for Partially Reconfigurable Systems.
ERSA 2010: 67-76 |
| 32 |  | Shaon Yousuf,
Ann Gordon-Ross:
DAPR: Design Automation for Partially Reconfigurable FPGAs.
ERSA 2010: 97-103 |
| 31 |  | Jeff Hiner,
Ashish Shenoy,
Roman L. Lysecky,
Susan Lysecky,
Ann Gordon-Ross:
Transaction-Level Modeling for Sensor Networks Using SystemC.
SUTC/UMC 2010: 197-204 |
| 30 |  | Arslan Munir,
Ann Gordon-Ross,
Susan Lysecky,
Roman L. Lysecky:
A lightweight dynamic optimization methodology for wireless sensor networks.
WiMob 2010: 129-136 |
| 29 |  | Ashish Shenoy,
Jeff Hiner,
Susan Lysecky,
Roman L. Lysecky,
Ann Gordon-Ross:
Evaluation of Dynamic Profiling Methodologies for Optimization of Sensor Networks.
Embedded Systems Letters 2(1): 10-13 (2010) |
| 28 |  | Arslan Munir,
Ann Gordon-Ross:
SIP-Based IMS Signaling Analysis for WiMax-3G Interworking Architectures.
IEEE Trans. Mob. Comput. 9(5): 733-750 (2010) |
| 2009 |
| 27 |  | Arslan Munir,
Ann Gordon-Ross:
An MDP-based application oriented optimal policy for wireless sensor networks.
CODES+ISSS 2009: 183-192 |
| 26 |  | Abelardo Jara-Berrocal,
Ann Gordon-Ross:
SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems.
DATE 2009: 268-273 |
| 25 |  | Adam Flynn,
Ann Gordon-Ross,
Alan D. George:
Bitstream relocation with local clock domains for partially reconfigurable FPGAs.
DATE 2009: 300-303 |
| 24 |  | Rafael Garcia,
Ann Gordon-Ross,
Alan D. George:
Exploiting Partially Reconfigurable FPGAs for Situation-Based Reconfiguration in Wireless Sensor Networks.
FCCM 2009: 243-246 |
| 23 |  | Rohit Kumar,
Ann Gordon-Ross:
Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs.
FPL 2009: 525-529 |
| 22 |  | Arslan Munir,
Ann Gordon-Ross:
SIP-Based IMS Registration Analysis for WiMax-3G Interworking Architectures.
ICNS 2009: 432-437 |
| 21 |  | Abelardo Jara-Berrocal,
Ann Gordon-Ross:
Runtime Temporal Partitioning Assembly to Reduce FPGA Reconfiguration Time.
ReConFig 2009: 374-379 |
| 20 |  | Weixun Wang,
Prabhat Mishra,
Ann Gordon-Ross:
SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems.
VLSI Design 2009: 547-552 |
| 19 |  | Ann Gordon-Ross,
Frank Vahid,
Nikil D. Dutt:
Fast Configurable-Cache Tuning With a Unified Second-Level Cache.
IEEE Trans. VLSI Syst. 17(1): 80-91 (2009) |
| 2008 |
| 18 |  | Ann Gordon-Ross,
Jeremy Lau,
Brad Calder:
Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy.
ACM Great Lakes Symposium on VLSI 2008: 379-382 |
| 17 |  | Pablo Viana,
Ann Gordon-Ross,
Edna Barros,
Frank Vahid:
A table-based method for single-pass cache optimization.
ACM Great Lakes Symposium on VLSI 2008: 71-76 |
| 16 |  | Chris Conger,
Ann Gordon-Ross,
Alan D. George:
Design Framework for Partial Run-Time FPGA Reconfiguration.
ERSA 2008: 122-128 |
| 15 |  | Karthik Sabhanatarajan,
Ann Gordon-Ross:
A resource efficient content inspection system for next generation Smart NICs.
ICCD 2008: 156-163 |
| 14 |  | Karthik Sabhanatarajan,
Ann Gordon-Ross,
Mark Oden,
Mukund Navada,
Alan D. George:
Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices.
ISVLSI 2008: 75-80 |
| 13 |  | Baoke Zhang,
Karthik Sabhanatarajan,
Ann Gordon-Ross,
Alan D. George:
Real-time performance analysis of Adaptive Link Rate.
LCN 2008: 282-288 |
| 2007 |
| 12 |  | Ann Gordon-Ross,
Frank Vahid:
A Self-Tuning Configurable Cache.
DAC 2007: 234-237 |
| 11 |  | Ann Gordon-Ross,
Pablo Viana,
Frank Vahid,
Walid A. Najjar,
Edna Barros:
A one-shot configurable-cache tuner for improved energy and performance.
DATE 2007: 755-760 |
| 2006 |
| 10 |  | Pablo Viana,
Ann Gordon-Ross,
Eamonn J. Keogh,
Edna Barros,
Frank Vahid:
Configurable cache subsetting for fast cache tuning.
DAC 2006: 695-700 |
| 2005 |
| 9 |  | Ann Gordon-Ross,
Frank Vahid,
Nikil Dutt:
A first look at the interplay of code reordering and configurable caches.
ACM Great Lakes Symposium on VLSI 2005: 416-421 |
| 8 |  | Ann Gordon-Ross,
Frank Vahid,
Nikil D. Dutt:
Fast configurable-cache tuning with a unified second-level cache.
ISLPED 2005: 323-326 |
| 7 |  | Ann Gordon-Ross,
Frank Vahid:
Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware.
IEEE Trans. Computers 54(10): 1203-1215 (2005) |
| 2004 |
| 6 |  | Ann Gordon-Ross,
Frank Vahid,
Nikil Dutt:
Automatic Tuning of Two-Level Caches to Embedded Applications.
DATE 2004: 208-213 |
| 2003 |
| 5 |  | Ann Gordon-Ross,
Frank Vahid:
Frequent loop detection using efficient non-intrusive on-chip hardware.
CASES 2003: 117-124 |
| 4 |  | Ann Gordon-Ross,
Susan Cotterell,
Frank Vahid:
Tiny instruction caches for low power embedded systems.
ACM Trans. Embedded Comput. Syst. 2(4): 449-481 (2003) |
| 2002 |
| 3 |  | Ann Gordon-Ross,
Frank Vahid:
Dynamic Loop Caching Meets Preloaded Loop Caching - A Hybrid Approach.
ICCD 2002: 446-449 |
| 2 |  | Ann Gordon-Ross,
Susan Cotterell,
Frank Vahid:
Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example.
Computer Architecture Letters 1: (2002) |
| 2001 |
| 1 |  | Frank Vahid,
Ann Gordon-Ross:
A self-optimizing embedded microprocessor using a loop table for low power.
ISLPED 2001: 219-224 |