Roberto Giorgi

	2012
29		Roberto Giorgi: TERAFLUX: exploiting dataflow parallelism in teradevices. Conf. Computing Frontiers 2012: 303-304
	2011
28		Antoni Portero, Zhibin Yu, Roberto Giorgi: TERAFLUX: Exploiting Tera-device Computing Challenges. Procedia CS 7: 146-147 (2011)
	2010
27		Massimo Alioto, Paolo Bennati, Roberto Giorgi: Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed. ISCAS 2010: 37-40
	2009
26		Roberto Giorgi, Zdravko Popovic, Nikola Puzovic: Introducing Hardware TLP Support in the Cell Processor. CISIS 2009: 657-662
25		Roberto Giorgi, Zdravko Popovic, Nikola Puzovic: Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture. IPDPS 2009: 1-8
24		Kyriakos Stavrou, Demos Pavlou, Marios Nikolaides, Panayiotis Petrides, Paraskevas Evripidou, Pedro Trancoso, Zdravko Popovic, Roberto Giorgi: Programming Abstractions and Toolchain for Dataflow Multithreading Architectures. ISPDC 2009: 107-114
23		Roberto Giorgi, Zdravko Popovic, Nikola Puzovic: Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture. SAMOS 2009: 78-87
	2008
22		Roberto Giorgi, Zdravko Popovic, Nikola Puzovic, Arnaldo Azevedo, Ben H. H. Juurlink: Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture. DSD 2008: 189-194
21		Roberto Giorgi, Paolo Bennati: Reducing Leakage through Filter Cache. DSD 2008: 334-341
20		Roberto Giorgi, Paolo Bennati: Filtering drowsy instruction cache to achieve better efficiency. SAC 2008: 1554-1555
19		Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli: Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2/sup m/). IEEE Trans. Computers 57(5): 672-685 (2008)
	2007
18		Roberto Giorgi, Zdravko Popovic, Nikola Puzovic: DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems. SBAC-PAD 2007: 263-270
	2006
17		Sandro Bartolini, Roberto Giorgi: Issues in Embedded Single-Chip Multicore Architectures. J. Embedded Computing 2(2): 137-139 (2006)
16		Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete: Memory performance: dealing with applications, systems and architecture. SIGARCH Computer Architecture News 34(1): 1-2 (2006)
	2005
15		Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete: Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload. J. Parallel Distrib. Comput. 65(3): 289-306 (2005)
	2004
14		Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli: A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields. SBAC-PAD 2004: 238-245
13		Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete: Speeding-up multiprocessors running DBMS workloads through coherence protocols. IJHPCN 1(1/2/3): 17-32 (2004)
12		Irina Branovic, Roberto Giorgi, Enrico Martinelli: A workload characterization of elliptic curve cryptography methods in embedded environments. SIGARCH Computer Architecture News 32(3): 27-34 (2004)
	2002
11		Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete: Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture. NETWORKING Workshops 2002: 134-146
	2001
10		Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete: Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload. HICSS 2001
9		Krishna M. Kavi, Joseph Arul, Roberto Giorgi: Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications. ISCA PDCS 2001: 365-371
8		Krishna M. Kavi, Roberto Giorgi, Joseph Arul: Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation. IEEE Trans. Computers 50(8): 834-846 (2001)
7		Sandro Bartolini, Roberto Giorgi, Jelica Protic, Cosimo Antonio Prete, M. Valero: Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. SIGARCH Computer Architecture News 29(5): 9-12 (2001)
	2000
6		Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete: Performance Analysis of Electronic Commerce Multiprocessor Server. HICSS 2000
5		Krishna M. Kavi, Joseph Arul, Roberto Giorgi: Execution and Cache Performance of the Scheduled Dataflow Architecture. J. UCS 6(10): 948-967 (2000)
	1999
4		Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete: Process Migration Effects on Memory Performance of Multiprocessor. HiPC 1999: 133-142
3		Roberto Giorgi, Cosimo Antonio Prete: PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors. IEEE Trans. Parallel Distrib. Syst. 10(7): 742-763 (1999)
	1997
2		Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi: A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors. HICSS (1) 1997: 266-275
	1996
1		Roberto Giorgi, Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina: A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors. EUROMICRO 1996: 207-214

Coauthor Index

1	Massimo Alioto	[27]
2	Joseph Arul	[5] [8] [9]
3	Arnaldo Azevedo (Arnaldo P. Azevedo Filho)	[22]
4	Sandro Bartolini	[7] [14] [16] [17] [19]
5	Paolo Bennati	[20] [21] [27]
6	Irina Branovic	[12] [14] [19]
7	Paraskevas Evripidou	[24]
8	Pierfrancesco Foglia	[4] [6] [10] [11] [13] [15] [16]
9	Ben H. H. Juurlink	[22]
10	Krishna M. Kavi	[5] [8] [9]
11	Enrico Martinelli	[12] [14] [19]
12	Marios Nikolaides	[24]
13	Demos Pavlou	[24]
14	Panayiotis Petrides	[24]
15	Zdravko Popovic	[18] [22] [23] [24] [25] [26]
16	Antoni Portero	[28]
17	Cosimo Antonio Prete	[1] [2] [3] [4] [6] [7] [10] [11] [13] [15] [16]
18	Gianpaolo Prina	[1] [2]
19	Jelica Protic	[7]
20	Nikola Puzovic	[18] [22] [23] [25] [26]
21	Luigi M. Ricciardi	[1] [2]
22	Kyriakos Stavrou	[24]
23	Pedro Trancoso	[24]
24	M. Valero	[7]
25	Zhibin Yu	[28]

Colors in the list of coauthors

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