Ran Ginosar

	2011
68		Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny: An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm. ISCAS 2011: 2593-2596
67		Ran Ginosar: Metastability and Synchronizers: A Tutorial. IEEE Design & Test of Computers 28(5): 23-35 (2011)
66		Dmitri Vainbrand, Ran Ginosar: Scalable network-on-chip architecture for configurable neural networks. Microprocessors and Microsystems - Embedded Hardware Design 35(2): 152-166 (2011)
	2010
65		Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman: Timing-driven variation-aware nonuniform clock mesh synthesis. ACM Great Lakes Symposium on VLSI 2010: 15-20
64		Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny: The Devolution of Synchronizers. ASYNC 2010: 94-103
63		Dmitri Vainbrand, Ran Ginosar: Network-on-Chip Architectures for Neural Networks. NOCS 2010: 135-144
62		Amit Berman, Ran Ginosar, Idit Keidar: Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip. VLSI-SoC 2010: 37-42
61		Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. IEEE Trans. VLSI Syst. 18(5): 689-696 (2010)
60		Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam Kolodny, Ran Ginosar: Asynchronous Current Mode Serial Communication. IEEE Trans. VLSI Syst. 18(7): 1107-1117 (2010)
59		Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. IEEE Trans. VLSI Syst. 18(8): 1262 (2010)
	2009
58		Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman: Power efficient tree-based crosslinks for skew reduction. ACM Great Lakes Symposium on VLSI 2009: 285-290
57		Asaf Baron, Ran Ginosar, Isaac Keslassy: The Capacity Allocation Paradox. INFOCOM 2009: 1359-1367
56		Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser: Multiple clock and voltage domains for chip multi processors. MICRO 2009: 459-468
55		Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny: QNoC asynchronous router. Integration 42(2): 103-115 (2009)
54		Rostislav (Reuven) Dobkin, Ran Ginosar: Two-phase synchronization with sub-cycle latency. Integration 42(3): 367-375 (2009)
	2008
53		Rostislav (Reuven) Dobkin, Ran Ginosar: Fast Universal Synchronizers. PATMOS 2008: 199-208
52		Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Timing optimization in logic with interconnect. SLIP 2008: 19-26
51		Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar: Parallel vs. serial on-chip communication. SLIP 2008: 43-50
50		A. Elyada, Ran Ginosar, Uri C. Weiser: Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors. IEEE Trans. VLSI Syst. 16(9): 1243-1248 (2008)
	2007
49		Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny: High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. ASYNC 2007: 3-14
48		Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Routing table minimization for irregular mesh NoCs. DATE 2007: 942-947
47		Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny: The Power of Priority: NoC Based Distributed Cache Coherency. NOCS 2007: 117-126
46		Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Access Regulation to Hot-Modules in Wormhole NoCs. NOCS 2007: 137-148
45		Rostislav (Reuven) Dobkin, Ran Ginosar, Israel Cidon: QNoC Asynchronous Router with Dynamic Virtual Channel Allocation. NOCS 2007: 218
44		Rami Rom, Jacob Erel, Michael Glikson, Randy A. Lieberman, Kobi Rosenblum, Ofer Binah, Ran Ginosar, David L. Hayes: Adaptive Cardiac Resynchronization Therapy Device Based on Spiking Neurons Architecture and Reinforcement Learning Scheme. IEEE Transactions on Neural Networks 18(2): 542-550 (2007)
43		Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Network Delays and Link Capacities in Application-Specific Wormhole NoCs. VLSI Design 2007: (2007)
	2006
42		Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny: Fast Asynchronous Shift Register for Bit-Serial Communication. ASYNC 2006: 117-127
41		Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Efficient link capacity and QoS design for network-on-chip. DATE 2006: 9-14
40		Uri Frank, Tsachy Kapschitz, Ran Ginosar: A predictive synchronizer for periodic clock domains. Formal Methods in System Design 28(2): 171-186 (2006)
39		Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou: High Rate Data Synchronization in GALS SoCs. IEEE Trans. VLSI Syst. 14(10): 1063-1074 (2006)
38		Ilya Obridko, Ran Ginosar: Minimal Energy Asynchronous Dynamic Adders. IEEE Trans. VLSI Syst. 14(9): 1043-1047 (2006)
	2005
37		Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar: An Asynchronous Router for Multiple Service Levels Networks on Chip. ASYNC 2005: 44-53
36		Tsachy Kapschitz, Ran Ginosar: Formal Verification of Synchronizers. CHARME 2005: 359-362
35		Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Low-leakage repeaters for NoC interconnects. ISCAS (1) 2005: 600-603
34		Ilya Obridko, Ran Ginosar: Low energy asynchronous architectures. ISCAS (5) 2005: 5238-5241
33		Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar: Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. IEEE Trans. VLSI Syst. 13(4): 427-438 (2005)
	2004
32		Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou: Data Synchronization Issues in GALS SoCs. ASYNC 2004: 170-180
31		Alex Branover, Rakefet Kol, Ran Ginosar: Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones. DATE 2004: 870-877
30		Uri Frank, Ran Ginosar: A Predictive Synchronizer for Periodic Clock Domains. PATMOS 2004: 402-412
29		Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar: Asynchronous gate-diffusion-input (GDI) circuits. IEEE Trans. VLSI Syst. 12(8): 847-856 (2004)
28		Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Cost considerations in network on chip. Integration 38(1): 19-42 (2004)
27		Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: QNoC: QoS architecture and design process for network on chip. Journal of Systems Architecture 50(2-3): 105-128 (2004)
	2003
26		Yaron Semiat, Ran Ginosar: Timing Measurements of Synchronization Circuits. ASYNC 2003: 68-77
25		Ran Ginosar: Fourteen Ways to Fool Your Synchronizer. ASYNC 2003: 89-97
24		Ken S. Stevens, Ran Ginosar, Shai Rotem: Relative timing [asynchronous design]. IEEE Trans. VLSI Syst. 11(1): 129-140 (2003)
23		Y. Elboim, Avinoam Kolodny, Ran Ginosar: A clock-tuning circuit for system-on-chip. IEEE Trans. VLSI Syst. 11(4): 616-626 (2003)
	1999
22		Ken S. Stevens, Shai Rotem, Ran Ginosar: Relative Timing. ASYNC 1999: 208-218
21		Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun: RAPPID: An Asynchronous Instruction Length Decoder. ASYNC 1999: 60-70
20		Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken: CAD Directions for High Performance Asynchronous Circuits. DAC 1999: 116-121
	1998
19		Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun: Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. ASYNC 1998: 80-
18		Uzi Zangi, Ran Ginosar: A low power video processor. ISLPED 1998: 136-138
17		Rakefet Kol, Ran Ginosar: Kin: A High Performance Asynchronous Processor Architecture. International Conference on Supercomputing 1998: 433-440
	1997
16		Rakefet Kol, Ran Ginosar: A Double-Latched Asynchronous Pipeline. ICCD 1997: 706-712
	1995
15		Ilana David, Ran Ginosar, Michael Yoeli: Self-timed is self-checking. J. Electronic Testing 6(2): 219-228 (1995)
	1993
14		Ilana David, Ran Ginosar, Michael Yoeli: Self-Timed Architecture of a Reduced Instruction Set Computer. Asynchronous Design Methodologies 1993: 29-43
13		Alan Rotman, Ran Ginosar: Control unit synthesis from a high-level language. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 162-167 (1993)
	1992
12		Ilana David, Ran Ginosar, Michael Yoeli: Implementing Sequential Machines as Self-Timed Circuits. IEEE Trans. Computers 41(1): 12-17 (1992)
11		Ilana David, Ran Ginosar, Michael Yoeli: An Efficient Implementation of Boolean Functions as Self-Timed Circuits. IEEE Trans. Computers 41(1): 2-11 (1992)
	1991
10		Arie Harsat, Ran Ginosar: CARMEL-4: The Unify-Spawn Machine for FCP. ICLP 1991: 840-854
	1990
9		Arie Harsat, Ran Ginosar: An Extended RISC Methodology and its Application to FCP. ICLP 1990: 67-82
8		Arie Harsat, Ran Ginosar: CARMEL-2: A second generation VLSI architecture for Flat Concurrent Prolog. New Generation Comput. 7(2-3): 197-218 (1990)
	1989
7		Ran Ginosar, David Egozi: Topological comparison of perfect shuffle and hypercube. International Journal of Parallel Programming 18(1): 37-68 (1989)
	1988
6		Arie Harsat, Ran Ginosar: CARMEL-2: A Second Generation VLSI Architecture for Flat Concurrent Prolog. FGCS 1988: 962-969
	1985
5		Ran Ginosar, Dwight D. Hill: Design and Implementation of Switching Systems for Parallel Processors. ICPP 1985: 674-680
	1983
4		Bruce W. Arden, Ran Ginosar: Performance evaluation of the MP/C. AFIPS National Computer Conference 1983: 539-555
	1982
3		Bruce W. Arden, Ran Ginosar: MP/C: A Multiprocessor/Computer Architecture. IEEE Trans. Computers 31(5): 455-473 (1982)
	1981
2		Bruce W. Arden, Ran Ginosar: A Single-Relation Module for a Data Base Machine. ISCA 1981: 227-238
1		Bruce W. Arden, Ran Ginosar: MP/C: A Multiprocessor/Computer Architecture. ISCA 1981: 3-20

Coauthor Index

1	Ameer Abdelhadi	[65]
2	Boris Agapiev	[21]
3	Bruce W. Arden	[1] [2] [3] [4]
4	Asaf Baron	[57]
5	Salomon Beer	[64] [68]
6	Peter A. Beerel	[19] [21]
7	Amit Berman	[62]
8	Ofer Binah	[44]
9	Evgeny Bolotin	[27] [28] [41] [43] [47] [48]
10	Alex Branover	[31]
11	Steven M. Burns	[20]
12	Wei-Chun Chou	[19]
13	Israel Cidon	[27] [28] [35] [41] [43] [45] [46] [47] [48]
14	Jordi Cortadella	[20]
15	Ilana David	[11] [12] [14] [15]
16	Charles Dike	[21]
17	Rostislav (Reuven) Dobkin	[32] [33] [37] [39] [42] [45] [49] [51] [53] [54] [55] [60] [64] [68]
18	David Egozi	[7]
19	Y. Elboim	[23]
20	A. Elyada	[50]
21	Jacob Erel	[44]
22	Uri Frank	[30] [40]
23	Eby G. Friedman	[52] [58] [59] [61] [65]
24	Eyal Friedman	[37]
25	Michael Glikson	[44]
26	Zvika Guz	[41] [43] [47]
27	Arie Harsat	[6] [8] [9] [10]
28	David L. Hayes	[44]
29	Dwight D. Hill	[5]
30	Tsachy Kapschitz	[36] [40]
31	Idit Keidar	[62]
32	Isaac Keslassy	[57]
33	Michael Kishinevsky	[20]
34	Rakefet Kol	[16] [17] [19] [21] [31]
35	Avinoam Kolodny	[23] [27] [28] [35] [41] [42] [43] [46] [47] [48] [49] [51] [52] [55] [58] [59] [60] [61] [64] [65] [68]
36	Randy A. Lieberman	[44]
37	Tuvia Liran	[49]
38	Avi Mendelson	[56]
39	Michael Moreinis	[29]
40	Arkadiy Morgenshtein	[29] [35] [51] [52] [59] [61]
41	Michael Moyal	[60]
42	Chris J. Myers	[19] [21]
43	Ilya Obridko	[34] [38]
44	Michael Peleg	[33]
45	Yevgeny Perelman	[49]
46	Michael Priel	[64] [68]
47	Rami Rom	[44]
48	Marly Roncken	[20] [21]
49	Kobi Rosenblum	[44]
50	Efraim Rotem	[56]
51	Shai Rotem	[19] [20] [21] [22] [24]
52	Alan Rotman	[13]
53	Yaron Semiat	[26]
54	Christos P. Sotiriou	[32] [39]
55	Kenneth S. Stevens (Ken S. Stevens)	[19] [20] [21] [22] [24]
56	Dmitri Vainbrand	[63] [66]
57	Inna Vaisband	[58]
58	Victoria Vishnyakov	[37]
59	Isask'har Walter	[41] [43] [46]
60	Uri C. Weiser	[50] [56]
61	Michael Yoeli	[11] [12] [14] [15]
62	Kenneth Y. Yun	[19] [21]
63	Uzi Zangi	[18]

Colors in the list of coauthors

Last update Fri Jun 1 15:44:53 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page