 | 2009 |
|---|
| 8 |       | Heinrich Wolf,
Horst A. Gieser,
Dirk Walter:
Investigating the CDM susceptibility of IC's at package and wafer level by capacitive coupled TLP.
Microelectronics Reliability 49(12): 1476-1481 (2009) |
| 2006 |
|---|
| 7 | | M. Etherton,
N. Qu,
J. Willemen,
Wolfgang Wilkening,
S. Mettler,
M. Dissegna,
R. Stella,
L. Zullino,
A. Andreini,
Horst A. Gieser:
Study of CDM specific effects for a smart power input protection structure.
Microelectronics Reliability 46(5-6): 666-676 (2006) |
| 6 | | Heinrich Wolf,
Horst A. Gieser,
Detlef Bonfert,
Markus Hauser:
ESD Susceptibility of Submicron Air Gaps.
Microelectronics Reliability 46(9-11): 1587-1590 (2006) |
| 5 | | Detlef Bonfert,
Horst A. Gieser,
Heinrich Wolf,
M. Frank,
A. Konrad,
J. Schulz:
Transient-induced latch-up test setup for wafer-level and package-level.
Microelectronics Reliability 46(9-11): 1629-1633 (2006) |
| 2005 |
|---|
| 4 | | Heinrich Wolf,
Horst A. Gieser,
Wolfgang Stadler,
Wolfgang Wilkening:
Capacitively coupled transmission line pulsing cc-TLP--a traceable and reproducible stress method in the CDM-domain.
Microelectronics Reliability 45(2): 279-285 (2005) |
| 3 | | S. Bargstädt-Franke,
Wolfgang Stadler,
Kai Esmark,
Martin Streibl,
Krzysztof Domanski,
Horst A. Gieser,
Heinrich Wolf,
W. Bala:
Transient latch-up: experimental analysis and device simulation.
Microelectronics Reliability 45(2): 297-304 (2005) |
| 2 | | Heinrich Wolf,
Horst A. Gieser,
Wolfgang Soldner,
Harald Gossner:
A Dedicated TLP Set-Up to Investigate the ESD Robustness of RF Elements and Circuits.
Microelectronics Reliability 45(9-11): 1421-1424 (2005) |
| 2003 |
|---|
| 1 | | Horst A. Gieser:
On-chip electrostatic discharge ESD.
Microelectronics Reliability 43(7): 985-986 (2003) |
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