Debjyoti Ghosh

	2005
5		Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy: Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. ISQED 2005: 453-458
4		Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy: Low-power scan design using first-level supply gating. IEEE Trans. VLSI Syst. 13(3): 384-395 (2005)
	2004
3		Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy: A Novel Low-Power Scan Design Technique Using Supply Gating. ICCD 2004: 60-65
2		Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy: A Technique to Reduce Power and Test Application Time in BIST. IOLTS 2004: 182-183
	2003
1		Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy: Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST. DFT 2003: 191-198

Coauthor Index

1	Swarup Bhunia	[1] [2] [3] [4] [5]
2	Hamid Mahmoodi (Hamid Mahmoodi-Meimand)	[3] [4] [5]
3	Saibal Mukhopadhyay	[3] [4]
4	Kaushik Roy	[1] [2] [3] [4] [5]

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