Abhijit Ghosh

	2000
27		Luc Séméria, Abhijit Ghosh: Methodology for hardware/software co-verification in C/C++ (short paper). ASP-DAC 2000: 405-408
26		Vivek Sinha, Frederic Doucet, Chuck Siska, Rajesh K. Gupta, Stan Y. Liao, Abhijit Ghosh: YAML: A Tool for Hardware Design Visualization and Capture. ISSS 2000: 9-17
25		Abhijit Ghosh, Ranga Vemuri: Formal Verification of Synthesized Mixed Signal Designs Using *BMDs. VLSI Design 2000: 84-
	1999
24		Abhijit Ghosh, Joachim Kunkel, Stan Y. Liao: Hardware Synthesis from C/C++. DATE 1999: 387-389
23		Abhijit Ghosh, Sandeep K. Lodha, Ranga Vemuri: Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops. Great Lakes Symposium on VLSI 1999: 140-143
22		Abhijit Ghosh, Ranga Vemuri: Formal Verification of Synthesized Analog Designs. ICCD 1999: 40-45
	1998
21		Fuchun Joseph Lin, Hong Liu, Abhijit Ghosh: A Methodology for Feature Interaction Detection in the AIN 0.1 Framework. IEEE Trans. Software Eng. 24(10): 797-817 (1998)
20		José C. Monteiro, Srinivas Devadas, Abhijit Ghosh: Sequential logic optimization for low power using input-disabling precomputation architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 279-284 (1998)
	1997
19		José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White: Estimation of average switching activity in combinational logic circuits using symbolic simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 121-127 (1997)
	1996
18		Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer: An observability-based code coverage metric for functional simulation. ICCAD 1996: 418-425
	1995
17		José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh: Optimization of combinational and sequential logic circuits for low power using precomputation. ARVLSI 1995: 430-444
16		Amelia Shen, Srinivas Devadas, Abhijit Ghosh: Probabilistic manipulation of Boolean functions using free Boolean diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 87-95 (1995)
	1994
15		Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou: Precomputation-based sequential logic optimization for low power. ICCAD 1994: 74-81
14		Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou: Precomputation-based sequential logic optimization for low power. IEEE Trans. VLSI Syst. 2(4): 426-436 (1994)
	1993
13		José C. Monteiro, Srinivas Devadas, Abhijit Ghosh: Retiming sequential circuits for low power. ICCAD 1993: 398-402
12		Amelia Shen, Srinivas Devadas, Abhijit Ghosh: Probabilistic construction and manipulation of free Boolean diagrams. ICCAD 1993: 544-583
11		Stan Y. Liao, Srinivas Devadas, Abhijit Ghosh: Boolean factorization using multiple-valued minimization. ICCAD 1993: 606-611
10		Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Sequential test generation and synthesis for testability at the register-transfer and logic levels. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 579-598 (1993)
	1992
9		Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer, Jacob White: Estimation of Average Switching Activity in Combinational and Sequential Circuits. DAC 1992: 253-259
8		Amelia Shen, Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer: On average power dissipation and random pattern testability of CMOS combinational logic networks. ICCAD 1992: 402-407
7		Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Heuristic minimization of Boolean relations using testing techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1166-1172 (1992)
	1991
6		Pranav Ashar, Abhijit Ghosh, Srinivas Devadas: Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams. ICCD 1991: 259-264
5		Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Test generation and verification for highly sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 652-667 (1991)
	1990
4		Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Verification of Interacting Sequential Circuits. DAC 1990: 213-219
3		Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Sequential Test Generation at the Register-Transfer and Logic Levels. DAC 1990: 580-586
2		Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. ICCAD 1990: 84-87
1		Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Sequential logic synthesis for testability using register-transfer level descriptions. ITC 1990: 274-283

Coauthor Index

1	Mazhar Alidina	[14] [15]
2	Pranav Ashar	[2] [6]
3	Srinivas Devadas	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
4	Frederic Doucet	[26]
5	Rajesh K. Gupta (Rajesh Gupta)	[26]
6	Kurt Keutzer	[8] [9] [18] [19]
7	Joachim Kunkel	[24]
8	Stan Y. Liao	[11] [24] [26]
9	Fuchun Joseph Lin	[21]
10	Hong Liu	[21]
11	Sandeep K. Lodha	[23]
12	José C. Monteiro (José Monteiro)	[13] [14] [15] [17] [19] [20]
13	A. Richard Newton	[1] [2] [3] [4] [5] [7] [10]
14	Marios C. Papaefthymiou	[14] [15]
15	John Rinderknecht	[17]
16	Luc Séméria	[27]
17	Amelia Shen	[8] [12] [16]
18	Vivek Sinha	[26]
19	Chuck Siska	[26]
20	Ranga Vemuri	[22] [23] [25]
21	Jacob K. White (Jacob White)	[9] [19]

Colors in the list of coauthors

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