 | 2011 |
|---|
| 9 |       | Prasun Ghosal,
Hafizur Rahaman,
Satrajit Das,
Arindam Das,
Parthasarathi Dasgupta:
Obstacle Aware Routing in 3D Integrated Circuits.
ADCONS 2011: 451-460 |
| 2010 |
|---|
| 8 | | Prasun Ghosal,
Hafizur Rahaman,
Parthasarathi Dasgupta:
Minimizing Thermal Disparities during Placement in 3D ICs.
CSE 2010: 160-167 |
| 7 | | Prasun Ghosal,
Malabika Biswas,
Manish Biswas:
Hardware Implementation of TDES Crypto System with On Chip Verification in FPGA
CoRR abs/1002.4836: (2010) |
| 2009 |
|---|
| 6 | | Tuhina Samanta,
Hafizur Rahaman,
Prasun Ghosal,
Parthasarathi Dasgupta:
A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment.
VLSI Design 2009: 387-392 |
| 2008 |
|---|
| 5 | | Prasun Ghosal,
Tuhina Samanta,
Hafizur Rahaman,
Parthasarathi Dasgupta:
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations.
ISVLSI 2008: 369-374 |
| 4 | | Tuhina Samanta,
Prasun Ghosal,
Hafizur Rahaman,
Parthasarathi Dasgupta:
Revisiting fidelity: a case of elmore-based Y-routing trees.
SLIP 2008: 27-34 |
| 2007 |
|---|
| 3 | | Tuhina Samanta,
Prasun Ghosal,
Hafizur Rahaman,
Parthasarathi Dasgupta:
Minimum-Congestion Placement for Y-interconnects: Some studies and observations.
ISVLSI 2007: 73-80 |
| 2006 |
|---|
| 2 | | Tuhina Samanta,
Prasun Ghosal,
Hafizur Rahaman,
Parthasarathi Dasgupta:
A heuristic method for constructing hexagonal Steiner minimal trees for routing in VLSI.
ISCAS 2006 |
| 2005 |
|---|
| 1 |  | Prasun Ghosal,
Tuhina Samanta,
Hafizur Rahaman,
Parthasarathi Dasgupta:
Recent Trends in the Application of Meta-Heuristics to VLSI Layout Design.
IICAI 2005: 232-251 |
Data released under the ODC-BY 1.0 license — See also our legal information page