G. Ghidini

	2009
15		M. Lanza, M. Porti, M. Nafría, X. Aymerich, G. Ghidini, A. Sebastiani: Trapped charge and stress induced leakage current (SILC) in tunnel SiO2 layers of de-processed MOS non-volatile memory devices observed at the nanoscale. Microelectronics Reliability 49(9-11): 1188-1191 (2009)
	2007
14		A. Sebastiani, R. Piagge, A. Modelli, G. Ghidini: High-K dielectrics for inter-poly application in non volatile memories. Microelectronics Reliability 47(4-5): 598-601 (2007)
13		J. Martín-Martínez, Simone Gerardin, R. Rodríguez, M. Nafría, X. Aymerich, A. Cester, Alessandro Paccagnella, G. Ghidini: Lifetime estimation of analog circuits from the electrical characteristics of stressed MOSFETs. Microelectronics Reliability 47(9-11): 1349-1352 (2007)
12		R. Bottini, S. Costantini, N. Galbiati, A. Ghetti, G. Ghidini, A. Mauri, C. Scozzari, A. Sebastiani: High voltage transistor degradation in NVM pump application. Microelectronics Reliability 47(9-11): 1384-1388 (2007)
	2006
11		Simone Gerardin, A. Griffoni, A. Cester, Alessandro Paccagnella, G. Ghidini: Degradation of static and dynamic behavior of CMOS inverters during constant and pulsed voltage stress. Microelectronics Reliability 46(9-11): 1669-1672 (2006)
	2005
10		G. Ghidini, M. Langenbuch, R. Bottini, D. Brazzelli, A. Ghetti, N. Galbiati, G. Giusto, A. Garavaglia: Impact of interface and bulk trapped charges on transistor reliability. Microelectronics Reliability 45(5-6): 857-860 (2005)
9		M. Langenbuch, R. Bottini, M. E. Vitali, G. Ghidini: In situ steam generation (ISSG) versus standard steam technology: impact on oxide reliability. Microelectronics Reliability 45(5-6): 875-878 (2005)
8		G. Ghidini, C. Capolupo, G. Giusto, A. Sebastiani, B. Stragliati, M. Vitali: Tunnel oxide degradation under pulsed stress. Microelectronics Reliability 45(9-11): 1337-1342 (2005)
	2003
7		G. Ghidini, A. Garavaglia, G. Giusto, A. Ghetti, R. Bottini, D. Peschiaroli, M. Scaravaggi, F. Cazzaniga, D. Ielmini: Impact of gate stack process on conduction and reliability of 0.18 mum PMOSFET. Microelectronics Reliability 43(8): 1221-1227 (2003)
6		A. Ghetti, D. Brazzelli, A. Benvenuti, G. Ghidini, A. Pavan: Anomalous gate oxide conduction on isolation edges: analysis and process optimization. Microelectronics Reliability 43(8): 1229-1235 (2003)
5		S. Cimino, A. Cester, Alessandro Paccagnella, G. Ghidini: Ionising radiation effects on MOSFET drain current. Microelectronics Reliability 43(8): 1247-1251 (2003)
	2002
4		G. Ghidini, D. Brazzelli: Evaluation methodology of thin dielectrics for non-volatile memory application. Microelectronics Reliability 42(9-11): 1473-1480 (2002)
3		E. Viganò, A. Ghetti, G. Ghidini, A. S. Spinelli: Post-breakdown characterization in thin gate oxides. Microelectronics Reliability 42(9-11): 1491-1496 (2002)
	2001
2		D. Brazzelli, G. Ghidini, C. Riva: Optimization of WSi2 by SiH4 CVD: impact on oxide quality. Microelectronics Reliability 41(7): 1003-1006 (2001)
1		N. Galbiati, G. Ghidini, C. Cremonesi, L. Larcher: Impact of the As dose in 0.35 mum EEPROM technology: characterization and modeling. Microelectronics Reliability 41(7): 999-1002 (2001)

Coauthor Index

1	X. Aymerich	[13] [15]
2	A. Benvenuti	[6]
3	R. Bottini	[7] [9] [10] [12]
4	D. Brazzelli	[2] [4] [6] [10]
5	C. Capolupo	[8]
6	F. Cazzaniga	[7]
7	A. Cester	[5] [11] [13]
8	S. Cimino	[5]
9	S. Costantini	[12]
10	C. Cremonesi	[1]
11	N. Galbiati	[1] [10] [12]
12	A. Garavaglia	[7] [10]
13	Simone Gerardin	[11] [13]
14	A. Ghetti	[3] [6] [7] [10] [12]
15	G. Giusto	[7] [8] [10]
16	A. Griffoni	[11]
17	D. Ielmini	[7]
18	M. Langenbuch	[9] [10]
19	M. Lanza	[15]
20	L. Larcher	[1]
21	J. Martín-Martínez	[13]
22	A. Mauri	[12]
23	A. Modelli	[14]
24	M. Nafría	[13] [15]
25	Alessandro Paccagnella	[5] [11] [13]
26	A. Pavan	[6]
27	D. Peschiaroli	[7]
28	R. Piagge	[14]
29	M. Porti	[15]
30	C. Riva	[2]
31	R. Rodríguez	[13]
32	M. Scaravaggi	[7]
33	C. Scozzari	[12]
34	A. Sebastiani	[8] [12] [14] [15]
35	A. S. Spinelli	[3]
36	B. Stragliati	[8]
37	E. Viganò	[3]
38	M. Vitali	[8]
39	M. E. Vitali	[9]

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