Tushar Gheewala

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1996

5 Sandeep Bhatia, Tushar Gheewala, Prab Varma: A Unifying Methodology for Intellectual Property and Custom Logic Testing. ITC 1996: 639-648

1994

4 Prab Varma, Tushar Gheewala: The economics of scan-path design for testability. J. Electronic Testing 5(2-3): 179-193 (1994)

1993

3 Prab Varma, Tushar Gheewala: Delay Testing Using a Matrix of Accessible Storage. ITC 1993: 243-252

1991

2 Susheel J. Chandra, Tom Ferry, Tushar Gheewala, Kerry Pierce: ATPG Based on a Novel Grid-Addressable Latch Element. DAC 1991: 282-286

1 Tushar Gheewala: For Test Automation, Silicon is Free. ITC 1991: 1111

	1996
5		Sandeep Bhatia, Tushar Gheewala, Prab Varma: A Unifying Methodology for Intellectual Property and Custom Logic Testing. ITC 1996: 639-648
	1994
4		Prab Varma, Tushar Gheewala: The economics of scan-path design for testability. J. Electronic Testing 5(2-3): 179-193 (1994)
	1993
3		Prab Varma, Tushar Gheewala: Delay Testing Using a Matrix of Accessible Storage. ITC 1993: 243-252
	1991
2		Susheel J. Chandra, Tom Ferry, Tushar Gheewala, Kerry Pierce: ATPG Based on a Novel Grid-Addressable Latch Element. DAC 1991: 282-286
1		Tushar Gheewala: For Test Automation, Silicon is Free. ITC 1991: 1111

Coauthor Index

1 Sandeep Bhatia [5]

2 Susheel J. Chandra [2]

3 Tom Ferry [2]

4 Kerry Pierce [2]

5 Prab Varma [3] [4] [5]

Colors in the list of coauthors

Last update Wed May 30 22:34:44 2012 CET by the DBLP Team —

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1	Sandeep Bhatia	[5]
2	Susheel J. Chandra	[2]
3	Tom Ferry	[2]
4	Kerry Pierce	[2]
5	Prab Varma	[3] [4] [5]