Amir Masoud Gharehbaghi

	2012
8		Amir Masoud Gharehbaghi, Masahiro Fujita: Transaction-based post-silicon debug of many-core System-on-Chips. ISQED 2012: 702-708
	2011
7		Amir Masoud Gharehbaghi, Masahiro Fujita: Formal verification guided automatic design error diagnosis and correction of complex processors. HLDVT 2011: 121-127
6		Amir Masoud Gharehbaghi, Masahiro Fujita: Global transaction ordering in Network-on-Chips for post-silicon validation. ISQED 2011: 284-289
	2010
5		Bijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita: Pipelined Microprocessors Optimization and Debugging. ARC 2010: 435-444
4		Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita: Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). FPGA 2010: 288
	2009
3		Masahiro Fujita, Yoshihisa Kojima, Amir Masoud Gharehbaghi: Debugging from high level down to gate level. DAC 2009: 627-630
2		Amir Masoud Gharehbaghi, Masahiro Fujita: Transaction-based debugging of system-on-chips with patterns. ICCD 2009: 186-192
	2007
1		Amir Masoud Gharehbaghi, Benyamin Hamdin Yaran, Shaahin Hessabi, Maziar Goudarzi: An assertion-based verification methodology for system-level design. Computers & Electrical Engineering 33(4): 269-284 (2007)

Coauthor Index

1	Bijan Alizadeh	[4] [5]
2	Masahiro Fujita	[2] [3] [4] [5] [6] [7] [8]
3	Maziar Goudarzi	[1]
4	Shaahin Hessabi	[1]
5	Yoshihisa Kojima	[3]
6	Benyamin Hamdin Yaran	[1]

Colors in the list of coauthors

Last update Wed May 30 22:34:44 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page