Andreas Gerstlauer

	2012
39		Andreas Gerstlauer, Suhas Chakravarty, Manan Kathuria, Parisa Razaghi: Abstract system-level models for early performance and power exploration. ASP-DAC 2012: 213-218
38		Parisa Razaghi, Andreas Gerstlauer: Automatic timing granularity adjustment for host-compiled software simulation. ASP-DAC 2012: 567-572
37		Parisa Razaghi, Andreas Gerstlauer: Predictive OS Modeling for Host-Compiled Simulation of Periodic Real-Time Task Sets. Embedded Systems Letters 4(1): 5-8 (2012)
	2011
36		Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn: A high-performance, low-power linear algebra core. ASAP 2011: 35-42
35		Rainer Dömer, Weiwei Chen, Xu Han, Andreas Gerstlauer: Multi-core parallel simulation of System-level Description Languages. ASP-DAC 2011: 311-316
34		Parisa Razaghi, Andreas Gerstlauer: Host-compiled multicore RTOS simulator for embedded real-time software development. DATE 2011: 222-227
33		Ku He, Andreas Gerstlauer, Michael Orshansky: Controlled timing-error acceptance for low energy IDCT design. DATE 2011: 758-763
32		Dylan Pfeifer, Andreas Gerstlauer: Expression-Level Parallelism for Distributed Spice Circuit Simulation. DS-RT 2011: 12-17
31		Jing Lin, Akshaya Srivatsa, Andreas Gerstlauer, Brian L. Evans: Heterogeneous multiprocessor mapping for real-time streaming systems. ICASSP 2011: 1605-1608
30		Ahmed Abdel-Hadi, Jonas Michel, Andreas Gerstlauer, Sriram Vishwanath: Real-Time Optimization of Video Transmission in a Network of AAVs. VTC Fall 2011: 1-5
	2010
29		Andreas Gerstlauer, Gunar Schirner: Platform modeling for exploration and synthesis. ASP-DAC 2010: 725-731
28		Gunar Schirner, Andreas Gerstlauer, Rainer Dömer: System-level development of embedded software. ASP-DAC 2010: 903-909
27		Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubühr, Jürgen Teich: A system-level synthesis approach from formal application models to generic bus-based MPSoCs. ICSAMOS 2010: 118-125
26		Andreas Gerstlauer: Host-compiled simulation of multi-core platforms. International Symposium on Rapid System Prototyping 2010: 1-6
25		Andreas Gerstlauer: Host-compiled simulation of multi-core platforms. International Symposium on Rapid System Prototyping 2010: 1-6
24		Gunar Schirner, Andreas Gerstlauer, Rainer Dömer: Fast and accurate processor models for efficient MPSoC design. ACM Trans. Design Autom. Electr. Syst. 15(2): (2010)
	2009
23		Rainer Dömer, Andreas Gerstlauer, Wolfgang Müller: Introduction to hardware-dependent software design hardware-dependent software for multi- and many-core embedded systems. ASP-DAC 2009: 290-292
22		Amal Banerjee, Andreas Gerstlauer: Transaction Level Modeling of Best-Effort Channels for Networked Embedded Devices. IESS 2009: 77-88
21		Ardavan Pedram, David Craven, Andreas Gerstlauer: Modeling Cache Effects at the Transaction Level. IESS 2009: 89-101
20		Andreas Gerstlauer, Christian Haubelt, Andy D. Pimentel, Todor Stefanov, Daniel D. Gajski, Jürgen Teich: Electronic System-Level Synthesis Methodologies. IEEE Trans. on CAD of Integrated Circuits and Systems 28(10): 1517-1530 (2009)
	2008
19		Gunar Schirner, Andreas Gerstlauer, Rainer Dömer: Automatic generation of hardware dependent software for MPSoCs from abstract system specifications. ASP-DAC 2008: 271-276
18		Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Daniel Gajski, A. Nakamura, Dai Araki, Y. Nishihara: Specify-explore-refine (SER): from specification to implementation. DAC 2008: 586-591
17		Rainer Dömer, Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Lukai Cai, Haobo Yu, Samar Abdi, Daniel D. Gajski: System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design. EURASIP J. Emb. Sys. 2008: (2008)
16		Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski: An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors. IEEE Trans. VLSI Syst. 16(4): 466-475 (2008)
	2007
15		Achim Rettberg, Mauro Cesar Zanella, Rainer Dömer, Andreas Gerstlauer, Franz-Josef Rammig: Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30 - June 1, 2007, Irvine, CA, USA Springer 2007
14		Gunar Schirner, Andreas Gerstlauer, Rainer Dömer: Abstract, Multifaceted Modeling of Embedded Processors for System Level Design. ASP-DAC 2007: 384-389
13		Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski: An Interactive Design Environment for C-based High-Level Synthesis. IESS 2007: 135-144
12		Gunar Schirner, Gautam Sachdeva, Andreas Gerstlauer, Rainer Dömer: Embedded Software Development in a System-Level Design Flow. IESS 2007: 289-298
11		Andreas Gerstlauer, Dongwan Shin, Junyu Peng, Rainer Dömer, Daniel Gajski: Automatic Layer-Based Generation of System-On-Chip Bus Communication Models. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1676-1687 (2007)
	2006
10		Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dömer, Daniel D. Gajski: Automatic generation of transaction level models for rapid design space exploration. CODES+ISSS 2006: 64-69
	2005
9		Andreas Gerstlauer, Dongwan Shin, Rainer Dömer, Daniel D. Gajski: System-level communication modeling for network-on-chip synthesis. ASP-DAC 2005: 45-48
8		Lukai Cai, Andreas Gerstlauer, Daniel Gajski: Multi-metric and multi-entity characterization of applications for early system design exploration. ASP-DAC 2005: 944-947
7		Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski: Automatic network generation for system-on-chip communication design. CODES+ISSS 2005: 255-260
	2004
6		Lukai Cai, Andreas Gerstlauer, Daniel Gajski: Retargetable profiling for rapid, early system-level design space exploration. DAC 2004: 281-286
	2003
5		Haobo Yu, Andreas Gerstlauer, Daniel Gajski: RTOS scheduling in transaction level models. CODES+ISSS 2003: 31-36
4		Andreas Gerstlauer, Haobo Yu, Daniel Gajski: RTOS Modeling for System Level Design. DATE 2003: 10130-10135
	2002
3		Rainer Dömer, Andreas Gerstlauer, Wolfgang Müller: The Formal Execution Semantics of SpecC. ISSS 2002: 150-155
2		Daniel Gajski, Andreas Gerstlauer: System-Level Abstraction Semantics. ISSS 2002: 231-236
	2000
1		Achim Rettberg, Franz J. Rammig, Andreas Gerstlauer, Daniel Gajski, Wolfram Hardt, Bernd Kleinjohann: The Specification Language SpecC within the PARADISE Design Environment. DIPES 2000: 111-120

Coauthor Index

1	Ahmed Abdel-Hadi	[30]
2	Samar Abdi	[17]
3	Dai Araki	[18]
4	Amal Banerjee	[22]
5	Lukai Cai	[6] [8] [17]
6	Suhas Chakravarty	[39]
7	Weiwei Chen	[35]
8	David Craven	[21]
9	Rainer Dömer	[3] [7] [9] [10] [11] [12] [13] [14] [15] [16] [17] [19] [23] [24] [28] [35]
10	Brian L. Evans	[31]
11	Daniel Gajski (Daniel D. Gajski)	[1] [2] [4] [5] [6] [7] [8] [9] [10] [11] [13] [16] [17] [18] [20]
12	Robert A. van de Geijn	[36]
13	Jens Gladigau	[27]
14	Xu Han	[35]
15	Wolfram Hardt	[1]
16	Christian Haubelt	[20] [27]
17	Ku He	[33]
18	Manan Kathuria	[39]
19	Bernd Kleinjohann	[1]
20	Jing Lin	[31]
21	Jonas Michel	[30]
22	Wolfgang Müller	[3] [23]
23	A. Nakamura	[18]
24	Y. Nishihara	[18]
25	Michael Orshansky	[33]
26	Ardavan Pedram	[21] [36]
27	Junyu Peng	[10] [11] [17] [18]
28	Dylan Pfeifer	[32]
29	Andy D. Pimentel	[20]
30	Franz Josef Rammig (Franz-Josef Rammig, Franz J. Rammig)	[1] [15]
31	Parisa Razaghi	[34] [37] [38] [39]
32	Achim Rettberg	[1] [15]
33	Gautam Sachdeva	[12]
34	Gunar Schirner	[12] [14] [19] [24] [28] [29]
35	Dongwan Shin	[7] [9] [10] [11] [13] [16] [17] [18]
36	Akshaya Srivatsa	[31]
37	Todor Stefanov	[20]
38	Martin Streubühr	[27]
39	Jürgen Teich	[20] [27]
40	Sriram Vishwanath	[30]
41	Haobo Yu	[4] [5] [17]
42	Mauro Cesar Zanella	[15]

Colors in the list of coauthors

Last update Wed May 30 22:34:44 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page