 | 2011 |
|---|
| 8 |       | Martin Wirnshofer,
Leonhard Heiß,
Georg Georgakos,
Doris Schmitt-Landsiedel:
A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring.
DDECS 2011: 261-266 |
| 2010 |
|---|
| 7 | | Dominik Lorenz,
Georg Georgakos,
Ulf Schlichtmann:
Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level (Alterungsanalyse von kombinatorischen Schaltungen auf Gatterebene).
it - Information Technology 52(4): 181-188 (2010) |
| 2009 |
|---|
| 6 | | Dominik Lorenz,
Georg Georgakos,
Ulf Schlichtmann:
Aging analysis of circuit timing considering NBTI and HCI.
IOLTS 2009: 3-8 |
| 2008 |
|---|
| 5 | | Florian Bauer,
Georg Georgakos,
Doris Schmitt-Landsiedel:
A Design Space Comparison of 6T and 8T SRAM Core-Cells.
PATMOS 2008: 116-125 |
| 2007 |
|---|
| 4 | | Franz X. Ruckerbauer,
Georg Georgakos:
Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena.
IOLTS 2007: 203-204 |
| 2004 |
|---|
| 3 | | Stephan Henzler,
Georg Georgakos,
Jörg Berthold,
Doris Schmitt-Landsiedel:
Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption.
PATMOS 2004: 392-401 |
| 2 | | Stephan Henzler,
Georg Georgakos,
Jörg Berthold,
Doris Schmitt-Landsiedel:
Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits.
PATMOS 2004: 789-798 |
| 2003 |
|---|
| 1 |  | Stephan Henzler,
Markus Koban,
Doris Schmitt-Landsiedel,
Jörg Berthold,
Georg Georgakos:
Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes.
VLSI-SOC 2003: 246-251 |
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