M. S. Gaur

	2011
7		Harsh Gidra, Israrul Haque, Nitin P. Kumar, M. Sargurunathan, M. S. Gaur, Vijay Laxmi, Mark Zwolinski, Virendra Singh: Parallelizing TUNAMI-N1 Using GPGPU. HPCC 2011: 845-850
6		Manas Kumar Puthal, Virendra Singh, M. S. Gaur, Vijay Laxmi: C-Routing: An adaptive hierarchical NoC routing methodology. VLSI-SoC 2011: 392-397
	2010
5		N. S. Vinay, Indira Rawaty, Erik Larsson, M. S. Gaur, Virendra Singh: Thermal aware test scheduling for stacked multi-chip-modules. EWDTS 2010: 343-349
4		K. R. Vinutha, Virendra Singh, Anzhela Matrosova, M. S. Gaur: Fault grading using Instruction-Execution graph. EWDTS 2010: 350-357
	2004
3		M. S. Gaur, Mark Zwolinski: Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique. VLSI Design 2004: 901-906
	2003
2		Mark Zwolinski, M. S. Gaur: Integrating testability with design space exploration. Microelectronics Reliability 43(5): 685-693 (2003)
	1997
1		Y. Narahari, N. Hemachandra, M. S. Gaur: Transient analysis of multiclass manufacturing systems with priority scheduling. Computers & OR 24(5): 387-398 (1997)

Coauthor Index

1	Harsh Gidra	[7]
2	Israrul Haque	[7]
3	N. Hemachandra	[1]
4	Nitin P. Kumar	[7]
5	Erik Larsson	[5]
6	Vijay Laxmi	[6] [7]
7	Anzhela Matrosova	[4]
8	Y. Narahari (Yadati Narahari)	[1]
9	Manas Kumar Puthal	[6]
10	Indira Rawaty	[5]
11	M. Sargurunathan	[7]
12	Virendra Singh	[4] [5] [6] [7]
13	N. S. Vinay	[5]
14	K. R. Vinutha	[4]
15	Mark Zwolinski	[2] [3] [7]

Colors in the list of coauthors

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