 | 2011 |
|---|
| 8 |       | Swapnil Bahl,
Roberto Mattiuzzo,
Shray Khullar,
Akhil Garg,
S. Graniello,
Khader S. Abdel-Hafez,
Salvatore Talluto:
State of the art low capture power methodology.
ITC 2011: 1-10 |
| 2010 |
|---|
| 7 | | Prashant Dubey,
Akhil Garg,
Shashank Mahajan:
Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time.
J. Electronic Testing 26(6): 659-666 (2010) |
| 2008 |
|---|
| 6 | | Akhil Garg,
Prashant Dubey:
On Chip Jitter Measurement through a High Accuracy TDC.
ISQED 2008: 844-847 |
| 5 | | Swapnil Bahl,
Rajiv Sarkar,
Akhil Garg:
Low Power Test.
ITC 2008: 1 |
| 2007 |
|---|
| 4 |  | Prashant Dubey,
Akhil Garg,
Sravan Kumar Bhaskarani:
Built in Defect Prognosis for Embedded Memories.
DDECS 2007: 167-172 |
| 3 | | Prashant Dubey,
Akhil Garg,
Sravan Kumar Bhaskarani:
GALS Based Shared Test Architecture for Embedded Memories.
ISCAS 2007: 157-160 |
| 2 | | Prashant Dubey,
Akhil Garg,
Sravan Kumar Bhaskarani:
Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis.
ISVLSI 2007: 171-178 |
| 2006 |
|---|
| 1 | | Akhil Garg,
Prashant Dubey:
Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost.
DFT 2006: 166-174 |
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