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| 2010 | ||
|---|---|---|
| 2 | S. Fransi, G. L. Farre, L. Garcia-Deiros, Salvador Manich: Design and implementation of Automatic Test Equipment IP module. European Test Symposium 2010: 244 | |
| 2007 | ||
| 1 | Salvador Manich, L. Garcia-Deiros, Joan Figueras: Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2046-2058 (2007) | |
| 1 | G. L. Farre | [2] |
| 2 | Joan Figueras | [1] |
| 3 | S. Fransi | [2] |
| 4 | Salvador Manich | [1] [2] |
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