Shuli Gao

	2011
8		Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini: Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs. ICECS 2011: 137-140
7		Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini: Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs. IPDPS Workshops 2011: 271-277
	2010
6		Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois: FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers. Signal Processing Systems 58(1): 3-15 (2010)
	2009
5		Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini: Two level decomposition based matrix multiplication for FPGAs. ICECS 2009: 427-430
4		Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini: Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs. Int. J. Reconfig. Comp. 2009: (2009)
	2007
3		Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois: FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. ASAP 2007: 18-23
2		Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois: Optimised realisations of large integer multipliers and squarers using embedded blocks. IET Computers & Digital Techniques 1(1): 9-16 (2007)
	2006
1		Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois: An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers. AICCSA 2006: 248-254

Coauthor Index

1	Dhamin Al-Khalili	[1] [2] [3] [4] [5] [6] [7] [8]
2	Noureddine Chabini	[1] [2] [3] [4] [5] [6] [7] [8]
3	J. M. Pierre Langlois	[1] [2] [3] [6]

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