Shantanu Ganguly

	1999
5		Qi Wang, Sarma B. K. Vrudhula, Gary K. H. Yeap, Shantanu Ganguly: Power reduction and power-delay trade-offs using logic transformations. ACM Trans. Design Autom. Electr. Syst. 4(1): 97-121 (1999)
	1997
4		Qi Wang, Sarma B. K. Vrudhula, Shantanu Ganguly: An Investigation of Power Delay Trade-Offs on PowerPC Circuits. DAC 1997: 425-428
3		Aurobindo Dasgupta, Shantanu Ganguly: Divide & Conquer: A Strategy for Synthesis of Low Power Finite State Machines. ICCD 1997: 740-745
2		Shantanu Ganguly, Daksh Lehther, Satyamurthy Pullela: Clock Distribution Methodology for PowerPCTM Microprocessors. VLSI Signal Processing 16(2-3): 181-189 (1997)
	1995
1		Shantanu Ganguly, Shervin Hojat: Clock distribution design and verification for PowerPC microprocessors. ICCAD 1995: 58-61

Coauthor Index

1	Aurobindo Dasgupta	[3]
2	Shervin Hojat	[1]
3	Daksh Lehther	[2]
4	Satyamurthy Pullela	[2]
5	Sarma B. K. Vrudhula	[4] [5]
6	Qi Wang	[4] [5]
7	Gary K. H. Yeap	[5]

Colors in the list of coauthors

Last update Wed May 30 22:34:44 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page