Malay K. Ganai

	2011
58		Malay K. Ganai: Scalable and precise symbolic analysis for atomicity violations. ASE 2011: 123-132
57		Malay K. Ganai, Nipun Arora, Chao Wang, Aarti Gupta, Gogul Balakrishnan: BEST: A symbolic testing tool for predicting multi-threaded program failures. ASE 2011: 596-599
56		Chao Wang, Malay K. Ganai: Predicting Concurrency Failures in the Generalized Execution Traces of x86 Executables. RV 2011: 4-18
55		Chao Wang, Sudipta Kundu, Rhishikesh Limaye, Malay K. Ganai, Aarti Gupta: Symbolic predictive analysis for concurrent programs. Formal Asp. Comput. 23(6): 781-805 (2011)
	2010
54		Sudipta Kundu, Malay K. Ganai, Chao Wang: Contessa: Concurrency Testing Augmented with Symbolic Analysis. CAV 2010: 127-131
53		Malay K. Ganai: Propelling SAT and SAT-based BMC using careset. FMCAD 2010: 231-238
52		Gogul Balakrishnan, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Vineet Kahlon, Weihong Li, Naoto Maeda, Nadia Papakonstantinou, Sriram Sankaranarayanan, Nishant Sinha, Chao Wang: Scalable and precise program analysis at NEC. FMCAD 2010: 273-274
51		Sicun Gao, Malay K. Ganai, Franjo Ivancic, Aarti Gupta, Sriram Sankaranarayanan, Edmund M. Clarke: Integrating ICP and LRA solvers for deciding nonlinear real arithmetic problems. FMCAD 2010: 81-89
50		Malay K. Ganai, Chao Wang, Weihong Li: Efficient state space exploration: Interleaving stateless and state-based model checking. ICCAD 2010: 786-793
49		Franjo Ivancic, Malay K. Ganai, Sriram Sankaranarayanan, Aarti Gupta: Numerical stability analysis of floating-point computations using software model checking. MEMOCODE 2010: 49-58
48		Malay K. Ganai, Chao Wang: Interval Analysis for Concurrent Trace Programs Using Transaction Sequence Graphs. RV 2010: 253-269
47		Chao Wang, Rhishikesh Limaye, Malay K. Ganai, Aarti Gupta: Trace-Based Symbolic Analysis for Atomicity Violations. TACAS 2010: 328-342
	2009
46		Chao Wang, Sudipta Kundu, Malay K. Ganai, Aarti Gupta: Symbolic Predictive Analysis for Concurrent Programs. FM 2009: 256-272
45		Malay K. Ganai, Franjo Ivancic: Efficient decision procedure for non-linear arithmetic constraints using CORDIC. FMCAD 2009: 61-68
44		Malay K. Ganai, Weihong Li: Bang for the buck: Improvising and scheduling verification engines for effective resource utilization. MEMOCODE 2009: 8-17
43		Malay K. Ganai, Sudipta Kundu: Reduction of Verification Conditions for Concurrent System Using Mutually Atomic Transactions. SPIN 2009: 68-87
	2008
42		Malay K. Ganai, Aarti Gupta: Tunneling and slicing: towards scalable BMC. DAC 2008: 137-142
41		Sudipta Kundu, Malay K. Ganai, Rajesh Gupta: Partial order reduction for scalable testing of systemC TLM designs. DAC 2008: 936-941
40		Malay K. Ganai, Aarti Gupta: Completeness in SMT-based BMC for Software Programs. DATE 2008: 831-836
39		Malay K. Ganai, Weihong Li: d-TSR: Parallelizing SMT-Based BMC Using Tunnels over a Distributed Framework. Haifa Verification Conference 2008: 194-199
38		Malay K. Ganai: Efficient Decision Procedure for Bounded Integer Non-linear Operations Using SMT(). Haifa Verification Conference 2008: 68-83
37		Chao Wang, Malay K. Ganai, Shuvendu K. Lahiri, Daniel Kroening: Embedded software verification: challenges and solutions. ICCAD 2008: 5
36		Gogul Balakrishnan, Malay K. Ganai: PED: Proof-Guided Error Diagnosis by Triangulation of Program Error Causes. SEFM 2008: 268-278
35		Malay K. Ganai, Aarti Gupta: Efficient Modeling of Concurrent Systems in BMC. SPIN 2008: 114-133
34		Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar: Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1513-1517 (2008)
33		Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Pranav Ashar: Efficient SAT-based bounded model checking for software verification. Theor. Comput. Sci. 404(3): 256-274 (2008)
	2007
32		Malay K. Ganai, Aarti Gupta: Efficient BMC for Multi-Clock Systems with Clocked Specifications. ASP-DAC 2007: 310-315
31		Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayashi: Synthesizing "Verification Aware" Models: Why and How? VLSI Design 2007: 50-56
30		Malay K. Ganai, Aarti Gupta, Pranav Ashar: Verification of Embedded Memory Systems using Efficient Memory Modeling CoRR abs/0710.4666: (2007)
29		Malay K. Ganai, Muralidhar Talupur, Aarti Gupta: SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in Solving Difference Logic. JSAT 3(1-2): 91-114 (2007)
	2006
28		Chao Wang, Aarti Gupta, Malay K. Ganai: Predicate learning and selective theory deduction for a difference logic solver. DAC 2006: 235-240
27		Malay K. Ganai, Aarti Gupta: Accelerating high-level bounded model checking. ICCAD 2006: 794-801
26		Aarti Gupta, Malay K. Ganai, Chao Wang: SAT-Based Verification Methods and Applications in Hardware Verification. SFM 2006: 108-143
25		Malay K. Ganai, Muralidhar Talupur, Aarti Gupta: SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in a Separation Logic Solver. TACAS 2006: 135-150
24		Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar: Efficient distributed SAT and SAT-based distributed Bounded Model Checking. STTT 8(4-5): 387-396 (2006)
	2005
23		Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar: F-Soft: Software Verification Platform. CAV 2005: 301-306
22		Malay K. Ganai, Aarti Gupta, Pranav Ashar: Beyond safety: customized SAT-based model checking. DAC 2005: 738-743
21		Malay K. Ganai, Aarti Gupta, Pranav Ashar: Verification of Embedded Memory Systems using Efficient Memory Modeling. DATE 2005: 1096-1101
20		Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta, Malay K. Ganai: Model Checking C Programs Using F-SOFT. ICCD 2005: 297-308
19		Chao Wang, Franjo Ivancic, Malay K. Ganai, Aarti Gupta: Deciding Separation Logic Formulae by SAT and Incremental Negative Cycle Elimination. LPAR 2005: 322-336
18		Himanshu Jain, Franjo Ivancic, Aarti Gupta, Malay K. Ganai: Localization and Register Sharing for Predicate Abstraction. TACAS 2005: 397-412
17		Malay K. Ganai, Aarti Gupta, Pranav Ashar: DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems. TACAS 2005: 575-580
16		Aarti Gupta, Malay K. Ganai, Pranav Ashar: Lazy Constraints and SAT Heuristics for Proof-Based Abstraction. VLSI Design 2005: 183-188
	2004
15		Malay K. Ganai, Aarti Gupta, Pranav Ashar: Efficient Modeling of Embedded Memories in Bounded Model Checking. CAV 2004: 440-452
14		Malay K. Ganai, Aarti Gupta, Pranav Ashar: Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. ICCAD 2004: 510-517
13		Pranav Ashar, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Zijiang Yang: Efficient SAT-based Bounded Model Checking for Software Verification. ISoLA (Preliminary proceedings) 2004: 157-164
	2003
12		Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar: Abstraction and BDDs Complement SAT-Based BMC in DiVer. CAV 2003: 206-209
11		Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar: Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking. CHARME 2003: 334-347
10		Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar: Learning from BDDs in SAT-based bounded model checking. DAC 2003: 824-829
9		Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar: Iterative Abstraction using SAT-based BMC with Proof Analysis. ICCAD 2003: 416-423
	2002
8		Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik: Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. DAC 2002: 747-750
7		Malay K. Ganai, Adnan Aziz: Improved SAT-Based Bounded Reachability Analysis. VLSI Design 2002: 729-734
6		Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K. Ganai: Robust Boolean reasoning for equivalence checking and functional property verification. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1377-1394 (2002)
	2001
5		Malay K. Ganai, Adnan Aziz: Rarity based guided state space search. ACM Great Lakes Symposium on VLSI 2001: 97-102
4		Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi: Circuit-based Boolean Reasoning. DAC 2001: 232-237
3		Malay K. Ganai, Praveen Yalagandula, Adnan Aziz, Andreas Kuehlmann, Vigyan Singhal: SIVA: A System for Coverage-Directed State Space Search. J. Electronic Testing 17(1): 11-27 (2001)
	1999
2		Malay K. Ganai, Adnan Aziz, Andreas Kuehlmann: Enhancing Simulation with BDDs and ATPG. DAC 1999: 385-390
1		Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns: Performance Driven Synthesis for Pass-Transistor Logic. VLSI Design 1999: 372-377

Coauthor Index

1	Nipun Arora	[57]
2	Pranav Ashar	[8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [21] [22] [23] [24] [30] [33] [34]
3	Adnan Aziz	[1] [2] [3] [5] [7]
4	Gogul Balakrishnan	[36] [52] [57]
5	Jeffrey L. Burns	[1]
6	Srihari Cadambi	[34]
7	Edmund M. Clarke	[51]
8	Sicun Gao	[51]
9	Aarti Gupta	[8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [40] [42] [46] [47] [49] [51] [52] [55] [57]
10	Rajesh K. Gupta (Rajesh Gupta)	[41]
11	Franjo Ivancic	[13] [18] [19] [20] [23] [33] [34] [45] [49] [51] [52]
12	Himanshu Jain	[18]
13	Vineet Kahlon	[52]
14	Daniel Kroening (Daniel Kröning)	[37]
15	Florian Krohm	[6]
16	Andreas Kuehlmann	[2] [3] [4] [6]
17	Sudipta Kundu	[41] [43] [46] [54] [55]
18	Shuvendu K. Lahiri	[37]
19	Weihong Li	[39] [44] [50] [52]
20	Rhishikesh Limaye	[47] [55]
21	Tai-Hung Liu	[1]
22	Naoto Maeda	[52]
23	Sharad Malik	[8]
24	Akira Mukaiyama	[31]
25	Nadia Papakonstantinou	[52]
26	Viresh Paruthi	[4] [6]
27	Sriram Sankaranarayanan	[49] [51] [52]
28	Ilya Shlyakhter	[20] [23] [34]
29	Vigyan Singhal	[3]
30	Nishant Sinha	[52]
31	Muralidhar Talupur	[25] [29]
32	Kazutoshi Wakabayashi	[31]
33	Chao Wang	[10] [12] [19] [26] [28] [37] [46] [47] [48] [50] [52] [54] [55] [56] [57]
34	Praveen Yalagandula	[3]
35	Zijiang Yang	[9] [10] [11] [12] [13] [23] [24] [33] [34]
36	Aleksandr Zaks	[34]
37	Lintao Zhang	[8]

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