Kwang-Jow Gan

	2011
12		Kwang-Jow Gan, Cher-Shiung Tsai, Yu-Kuang Li, Jenq-Jong Lu: Logic circuit design using monostable-bistable transition logic element based on standard BiCMOS process. Microelectronics Journal 42(2): 477-482 (2011)
	2010
11		Kwang-Jow Gan, Dong-Shong Liang: Investigation of Adjustable Current-Voltage Characteristics and Hysteresis Phenomena for Multiple-Peak Negative Differential Resistance Circuit. IEICE Transactions 93-C(4): 514-520 (2010)
10		Kwang-Jow Gan, Dong-Shong Liang, Yan-Wun Chen: Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources. IEICE Transactions 93-D(8): 2068-2072 (2010)
	2009
9		Dong-Shong Liang, Kwang-Jow Gan, Jenq-Jong Lu, Cheng-Chi Tai, Cher-Shiung Tsai, Geng-Huang Lan, Yaw-Hwang Chen: Multiple-Valued Memory Design by Standard BiCMOS Technique. CSIE (3) 2009: 596-599
8		Dong-Shong Liang, Kwang-Jow Gan, Cheng-Chi Tai, Cher-Shiung Tsai: Standard BiCMOS Implementation of a Two-Peak Negative Differential Resistance Circuit with High and Adjustable Peak-to-Valley Current Ratio. IEICE Transactions 92-C(5): 635-638 (2009)
	2008
7		Dong-Shong Liang, Kwang-Jow Gan: New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits. DELTA 2008: 258-261
	2006
6		Dong-Shong Liang, Cheng-Chi Tai, Kwang-Jow Gan, Cher-Shiung Tsai, Yaw-Hwang Chen: Design of AND and NAND Logic Gate Using NDR-BASED Circuit Suitable for CMOS Process. APCCAS 2006: 1325-1328
5		Kwang-Jow Gan, Dong-Shong Liang, Cher-Shiung Tsai, Yaw-Hwang Chen, Chun-Ming Wen: Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS Process. APCCAS 2006: 1476-1479
4		Dong-Shong Liang, Yaw-Hwang Chen, Chun-Min Wen, Chun-Da Tu, Kwang-Jow Gan, Cher-Shiung Tsai: The Design of MOS-NDR-Based Cellular Neural Network. IJCNN 2006: 1033-1035
	2005
3		Dong-Shong Liang, Kwang-Jow Gan, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, Long-Xian Su: Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits. IWSOC 2005: 372-375
2		Kwang-Jow Gan, Dong-Shong Liang, Chung-Chih Hsiao, Shih-Yu Wang, Feng-Chang Chiang, Cher-Shiung Tsai, Yaw-Hwang Chen, Shun-Huo Kuo, Chi-Pin Chen: Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process. IWSOC 2005: 392-395
1		Dong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang: Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits. IWSOC 2005: 78-81

Coauthor Index

1	Chi-Pin Chen	[1] [2]
2	Yan-Wun Chen	[10]
3	Yaw-Hwang Chen	[1] [2] [3] [4] [5] [6] [9]
4	Feng-Chang Chiang	[1] [2] [3]
5	Chung-Chih Hsiao	[1] [2] [3]
6	Shun-Huo Kuo	[1] [2] [3]
7	Geng-Huang Lan	[9]
8	Yu-Kuang Li	[12]
9	Dong-Shong Liang	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
10	Jenq-Jong Lu	[9] [12]
11	Long-Xian Su	[1] [3]
12	Cheng-Chi Tai	[6] [8] [9]
13	Cher-Shiung Tsai	[1] [2] [3] [4] [5] [6] [8] [9] [12]
14	Chun-Da Tu	[4]
15	Shih-Yu Wang	[1] [2] [3]
16	Chun-Min Wen	[4]
17	Chun-Ming Wen	[5]

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