 | 2009 |
|---|
| 5 |       | Krishna Chakravadhanula,
Vivek Chickermane,
Brion L. Keller,
Patrick R. Gallagher Jr.,
Anis Uzzaman:
Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?.
Asian Test Symposium 2009: 295-300 |
| 4 | | Krishna Chakravadhanula,
Vivek Chickermane,
Brion L. Keller,
Patrick R. Gallagher Jr.,
Prashant Narang:
Capture power reduction using clock gating aware test generation.
ITC 2009: 1-9 |
| 2008 |
|---|
| 3 | | Vivek Chickermane,
Patrick R. Gallagher Jr.,
James Sage,
Paul Yuan,
Krishna Chakravadhanula:
A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs.
ITC 2008: 1-10 |
| 2001 |
|---|
| 2 | | Patrick R. Gallagher Jr.,
Vivek Chickermane,
Steven Gregor,
Thomas S. Pierre:
A building block BIST methodology for SOC designs: a case study.
ITC 2001: 111-120 |
| 1993 |
|---|
| 1 |  | Patrick R. Gallagher Jr.:
The Evolution of IT Security Convergence.
SEC 1993: 13-22 |
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