Sezer Gören

	2011
14		Sezer Gören, Ozgur Ozkurt, Abdullah Yildiz, H. Fatih Ugurdag: FPGA bitstream protection with PUFs, obfuscation, and multi-boot. ReCoSoC 2011: 1-2
13		Sezer Gören, H. Fatih Ugurdag, Okan Palaz: Defect-Aware Nanocrossbar Logic Mapping through Matrix Canonization Using Two-Dimensional Radix Sort. JETC 7(3): 12 (2011)
	2010
12		Sezer Gören, H. Fatih Ugurdag, Okan Palaz: Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonization. European Test Symposium 2010: 246
11		Sezer Gören, H. Fatih Ugurdag, Abdullah Yildiz, Ozgur Ozkurt: FPGA design security with time division multiplexed PUFs. HPCS 2010: 608-614
10		Sezer Gören, H. Fatih Ugurdag, Okan Palaz: Defect-Tolerant Logic Mapping for Nanocrossbars Based on Two-Dimensional Sort. ISCIS 2010: 399-404
9		H. Fatih Ugurdag, Sezer Gören, Ferhat Canbay: Gravitational pose estimation. Computers & Electrical Engineering 36(6): 1165-1180 (2010)
	2009
8		Sezer Gören: Optimization of Embedded Controllers Based on Redundant Transition Removal and Fault Simulation Using k-WISE Tests. Journal of Circuits, Systems, and Computers 18(4): 647-663 (2009)
	2007
7		Sezer Gören, F. Joel Ferguson: On state reduction of incompletely specified finite state machines. Computers & Electrical Engineering 33(1): 58-69 (2007)
	2006
6		H. Fatih Ugurdag, Yahya Sahin, Onur Baskirt, Soner Dedeoglu, Sezer Gören, Yasar S. Kocak: Population-Based FPGA Solution to Mastermind Game. AHS 2006: 237-246
5		Sezer Gören, F. Joel Ferguson: Test sequence generation for controller verification and test with high coverage. ACM Trans. Design Autom. Electr. Syst. 11(4): 916-938 (2006)
	2002
4		Sezer Gören, F. Joel Ferguson: CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines. DATE 2002: 248-254
3		Sezer Gören, F. Joel Ferguson: Testing Finite State Machines Based on a Structural Coverage Metric . ITC 2002: 773-780
	1999
2		Pak K. Chan, Mark J. Boyd, Sezer Gören, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, K. Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu: Reducing Compilation Time of Zhong's FPGA-Based SAT Solver. FCCM 1999: 308-309
1		Sezer Gören, F. Joel Ferguson: Checking sequence generation for asynchronous sequential elements. ITC 1999: 406-413

Coauthor Index

1	Onur Baskirt	[6]
2	Mark J. Boyd	[2]
3	Ferhat Canbay	[9]
4	Pak K. Chan	[2]
5	Soner Dedeoglu	[6]
6	F. Joel Ferguson	[1] [3] [4] [5] [7]
7	K. Klenk	[2]
8	Yasar S. Kocak	[6]
9	V. Kodavati	[2]
10	R. Kundu	[2]
11	M. Margolese	[2]
12	Ozgur Ozkurt	[11] [14]
13	Okan Palaz	[10] [12] [13]
14	Yahya Sahin	[6]
15	J. Sun	[2]
16	K. Suzuki	[2]
17	E. Thorne	[2]
18	H. Fatih Ugurdag	[6] [9] [10] [11] [12] [13] [14]
19	X. Wang	[2]
20	J. Xu	[2]
21	Abdullah Yildiz	[11] [14]
22	M. Zhu	[2]

Colors in the list of coauthors

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