 | 2011 |
|---|
| 8 |       | Masanori Furuta,
Mai Nozawa,
Tetsuro Itakura:
A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique.
J. Solid-State Circuits 46(6): 1360-1370 (2011) |
| 2010 |
|---|
| 7 | | Masanori Furuta,
Mai Nozawa,
Tetsuro Itakura:
A 0.06mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS.
ISSCC 2010: 382-383 |
| 2008 |
|---|
| 6 | | Masanori Furuta,
Takafumi Yamaji,
Takeshi Ueno,
Tetsuro Itakura:
An area-efficient sampling rate converter using negative feedback technique.
ISCAS 2008: 1922-1925 |
| 2007 |
|---|
| 5 | | Masanori Furuta,
Shoji Kawahito,
Daisuke Miyazaki:
A Digital-Calibration Technique for Redundant Radix-4 Pipelined Analog-to-Digital Converters.
IEEE T. Instrumentation and Measurement 56(6): 2301-2311 (2007) |
| 2006 |
|---|
| 4 | | Kazutaka Honda,
Masanori Furuta,
Shoji Kawahito:
A 1V 10b 125MSample/s A/D Converter Using Cascade Amp-Sharing and Capacitance Coupling Techniues.
ISCAS 2006: 1031-1034 |
| 3 | | Zheng Liu,
Masanori Furuta,
Shoji Kawahito:
Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits.
IEICE Transactions 89-C(6): 710-716 (2006) |
| 2005 |
|---|
| 2 | | Shoji Kawahito,
Kazutaka Honda,
Masanori Furuta,
Nobuhiro Kawai,
Daisuke Miyazaki:
Low-Power Design of High-Speed A/D Converters.
IEICE Transactions 88-C(4): 468-478 (2005) |
| 2003 |
|---|
| 1 | | Atsushi Suzuki,
Shoji Kawahito,
Daisuke Miyazaki,
Masanori Furuta:
A digitally skew correctable multi-phase clock generator using a master-slave DLL.
ISCAS (1) 2003: 105-108 |
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