Hiroshi Fuketa

	2012
16		Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai: 24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits. ISQED 2012: 586-591
15		Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Makoto Takamiya, Hiroshi Toshiyoshi, Takao Someya, Takayasu Sakurai: Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits. ISSCC 2012: 308-310
14		Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai: 13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. ISSCC 2012: 486-488
13		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. IEEE Trans. VLSI Syst. 20(2): 333-343 (2012)
	2011
12		Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai: A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates. DAC 2011: 984-989
11		Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai: 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics. ISLPED 2011: 163-168
10		Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai: Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. ISLPED 2011: 21-26
9		Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye: An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion. IEEE Trans. on Circuits and Systems 58-II(5): 299-303 (2011)
	2010
8		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. ASP-DAC 2010: 361-362
7		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits. IEEE Trans. VLSI Syst. 18(7): 1118-1129 (2010)
	2009
6		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. ASP-DAC 2009: 266-271
5		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. CICC 2009: 215-218
4		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction. IEICE Transactions 92-A(12): 3094-3102 (2009)
3		Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability. IEICE Transactions 92-C(2): 281-285 (2009)
	2008
2		Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. ACM Great Lakes Symposium on VLSI 2008: 387-390
1		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. ISLPED 2008: 3-8

Coauthor Index

1	Koichi Hamamoto	[2] [3]
2	Masanori Hashimoto	[1] [2] [3] [4] [5] [6] [7] [8] [9] [13]
3	Koji Hirairi	[10] [11] [14] [16]
4	Kentaro Honda	[15]
5	Tsung-Ching Huang	[15]
6	Satoshi Iida	[10] [12]
7	Koichi Ishida	[15]
8	Hagen Klauk	[15]
9	Dan Kuroda	[9]
10	Yukio Mitsuyama	[1] [2] [3] [4] [5] [6] [7] [8] [13]
11	Atsushi Muramatsu	[16]
12	Masahiro Nomura	[10] [11] [12] [14] [16]
13	Yasuyuki Okuma	[14]
14	Takao Onoye	[1] [2] [3] [4] [5] [6] [7] [8] [9] [13]
15	Yu Pu	[16]
16	Takayasu Sakurai	[10] [11] [12] [14] [15] [16]
17	Masato Sasaki	[16]
18	Tsuyoshi Sekitani	[15]
19	Hirofumi Shinohara	[11] [12] [14] [16]
20	Yasuhiro Shinozuka	[15]
21	Takao Someya	[15]
22	Ryo Takahashi	[16]
23	Makoto Takamiya	[10] [11] [12] [14] [15] [16]
24	Gregory Tortissier	[15]
25	Hiroshi Toshiyoshi	[15]
26	Tadashi Yasufuku	[10] [11] [12] [14] [16]
27	Tomoyuki Yokota	[15]
28	Yun Fei Zheng	[16]
29	Ute Zschieschang	[15]

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