Kunihiro Fujiyoshi

	2011
28		Kunihiro Fujiyoshi, Keisuke Ishihara, Tan Wei Liang: A novel representation for repeated placement. ISCAS 2011: 2869-2872
	2010
27		Hidenori Ohta, Toshinori Yamada, Kunihiro Fujiyoshi: On the Number of Rooms in a Rectangular Solid Dissection. JIP 18: 138-146 (2010)
	2009
26		Hidenori Ohta, Kunihiro Fujiyoshi: Representation of 3D-LSI Floorplan based on Stacked-rectangular-dissection. ISCAS 2009: 1731-1734
25		Kunihiro Fujiyoshi, Hidenori Kawai, Keisuke Ishihara: A Tree Based Novel Representation for 3D-Block Packing. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 759-764 (2009)
24		Natsumi Hirakawa, Kunihiro Fujiyoshi: Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation. IEICE Transactions 92-A(2): 467-474 (2009)
	2008
23		Hidenori Ohta, Toshinori Yamada, Chikaaki Kodama, Kunihiro Fujiyoshi: The O-Sequence: Representation of 3D-Dissection. IEICE Transactions 91-A(8): 2111-2119 (2008)
	2007
22		Kunihiro Fujiyoshi, Hidenori Kawai, Keisuke Ishihara: DTS: A Tree Based Representation for 3D-Block Packing. ISCAS 2007: 1045-1048
21		Shinichi Koda, Chikaaki Kodama, Kunihiro Fujiyoshi: Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 659-668 (2007)
20		Kunihiro Fujiyoshi, Chikaaki Kodama, Akira Ikeda: A fast algorithm for rectilinear block packing based on selected sequence-pair. Integration 40(3): 274-284 (2007)
	2006
19		N. Okada, Chikaaki Kodama, T. Sato, Kunihiro Fujiyoshi: Thermal Driven Module Placement Using Sequence-pair. APCCAS 2006: 1871-1874
18		Yukihide Kohira, Chikaaki Kodama, Kunihiro Fujiyoshi, Atsushi Takahashi: Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems. ISCAS 2006
17		Shinichi Kouda, Chikaaki Kodama, Kunihiro Fujiyoshi: Improved method of cell placement with symmetry constraints for analog IC layout design. ISPD 2006: 192-199
	2005
16		Hiroaki Itoga, Chikaaki Kodama, Kunihiro Fujiyoshi: A Graph Based Soft Module Handling in Floorplan. IEICE Transactions 88-A(12): 3390-3397 (2005)
15		Chikaaki Kodama, Kunihiro Fujiyoshi: Minimizing the Number of Empty Rooms on Floorplan by Dissection Line Merge. IEICE Transactions 88-D(7): 1389-1396 (2005)
	2004
14		Chikaaki Kodama, Kunihiro Fujiyoshi, Teppei Koga: A novel encoding method into sequence-pair. ISCAS (5) 2004: 329-332
	2002
13		H. Saito, K. Wakata, Kunihiro Fujiyoshi, K. Sakanushi, T. Obata: An improved method of convex-shaped block packing based on sequence-pair [VLSI layout]. APCCAS (2) 2002: 125-130
12		Chikaaki Kodama, Kunihiro Fujiyoshi: An efficient decoding method of sequence-pair. APCCAS (2) 2002: 131-136
	2000
11		Kunihiro Fujiyoshi, Hiroshi Murata: Arbitrary convex and concave rectilinear block packing usingsequence-pair. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 224-233 (2000)
	1999
10		Kunihiro Fujiyoshi, Hiroshi Murata: Arbitrary convex and concave rectilinear block packing using sequence-pair. ISPD 1999: 103-110
	1998
9		Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko: VLSI/PCB placement with obstacles based on sequence pair. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 60-68 (1998)
8		Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani: Module packing based on the BSG-structure and IC layout applications. IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 519-530 (1998)
	1997
7		Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko: VLSI/PCB placement with obstacles based on sequence-pair. ISPD 1997: 26-31
6		Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu: Design of minimum and uniform bipartites for optimum connection blocks of FPGA. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1377-1383 (1997)
	1996
5		Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani: Module placement on BSG-structure and IC layout applications. ICCAD 1996: 484-491
4		Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani: VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1518-1524 (1996)
	1995
3		Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani: Rectangle-packing-based module placement. ICCAD 1995: 472-479
	1994
2		Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu: The Totally-Perfect Bipartite Graph and Its Construction. ISAAC 1994: 541-549
1		Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu: Design of Optimum Totally Perfect Connection-Blocks of FPGA. ISCAS 1994: 221-224

Coauthor Index

1	Natsumi Hirakawa	[24]
2	Akira Ikeda	[20]
3	Keisuke Ishihara	[22] [25] [28]
4	Hiroaki Itoga	[16]
5	Yoji Kajitani	[1] [2] [3] [4] [5] [6] [8]
6	Mineo Kaneko	[7] [9]
7	Hidenori Kawai	[22] [25]
8	Shinichi Koda	[21]
9	Chikaaki Kodama	[12] [14] [15] [16] [17] [18] [19] [20] [21] [23]
10	Teppei Koga	[14]
11	Yukihide Kohira	[18]
12	Shinichi Kouda	[17]
13	Tan Wei Liang	[28]
14	Hiroshi Murata	[3] [4] [5] [7] [8] [9] [10] [11]
15	Shigetoshi Nakatake	[3] [4] [5] [8]
16	Hiroshi Niitsu	[1] [2] [6]
17	T. Obata	[13]
18	Hidenori Ohta	[23] [26] [27]
19	N. Okada	[19]
20	H. Saito	[13]
21	K. Sakanushi	[13]
22	T. Sato	[19]
23	Atsushi Takahashi	[18]
24	K. Wakata	[13]
25	Toshinori Yamada	[23] [27]

Colors in the list of coauthors

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