Hideo Fujiwara

	2011
212		Hideo Fujiwara, Katsuya Fujiwara, Hideo Tamamoto: Secure scan design using shift register equivalents against differential behavior attack. ASP-DAC 2011: 818-823
211		Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara: Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. European Test Symposium 2011: 147-152
210		Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara: F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG. European Test Symposium 2011: 203
209		Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara: Temperature-Variation-Aware Test Pattern Optimization. European Test Symposium 2011: 214
208		Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara: Faster-than-at-speed test for increased test quality and in-field reliability. ITC 2011: 1-9
207		Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara: F-Scan: A DFT Method for Functional Scan at RTL. IEICE Transactions 94-D(1): 104-113 (2011)
206		Katsuya Fujiwara, Hideo Fujiwara, Hideo Tamamoto: Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design. IEICE Transactions 94-D(7): 1430-1439 (2011)
205		Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara: Balanced Secure Scan: Partial Scan Approach for Secret Information Protection. J. Electronic Testing 27(2): 99-108 (2011)
204		Chia Yee Ooi, Hideo Fujiwara: A New Design-for-Testability Method Based on Thru-Testability. J. Electronic Testing 27(5): 583-598 (2011)
	2010
203		Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara: Graph theoretic approach for scan cell reordering to minimize peak shift power. ACM Great Lakes Symposium on VLSI 2010: 73-78
202		Hideo Fujiwara, Marie Engelene J. Obien: Secure and testable scan design using extended de Bruijn graphs. ASP-DAC 2010: 413-418
201		Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara: Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits. Asian Test Symposium 2010: 206-211
200		Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara: Seed Ordering and Selection for High Quality Delay Test. Asian Test Symposium 2010: 313-318
199		Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara: Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power. Asian Test Symposium 2010: 371-374
198		Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, Hideo Tamamoto: SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan design. DDECS 2010: 193-196
197		Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara: A synthesis method to propagate false path information from RTL to gate level. DDECS 2010: 197-200
196		Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara: Enabling False Path Identification from RTL for Reducing Design and Test Futileness. DELTA 2010: 20-25
195		Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara: Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. European Test Symposium 2010: 259
194		Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara: Test pattern selection to optimize delay test quality with a limited size of test set. European Test Symposium 2010: 260
193		Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara: Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS 2010: 21-26
192		Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara: Constrained ATPG for functional RTL circuits using F-Scan. ITC 2010: 615-624
191		Alodeep Sanyal, Krishnendu Chakrabarty, Mahmut Yilmaz, Hideo Fujiwara: RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage. ITC 2010: 625-634
190		Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh: On Minimization of Test Application Time for RAS. VLSI Design 2010: 393-398
189		Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara: Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. VTS 2010: 188-193
188		Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara: A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. IEICE Transactions 93-D(1): 24-32 (2010)
187		Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara: Design and Optimization of Transparency-Based TAM for SoC Test. IEICE Transactions 93-D(6): 1549-1559 (2010)
186		Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara: A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification. IEICE Transactions 93-D(7): 1857-1865 (2010)
185		Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara: RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences. J. Electronic Testing 26(2): 151-164 (2010)
	2009
184		Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara: Fast false path identification based on functional unsensitizability using RTL information. ASP-DAC 2009: 660-665
183		Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara: Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. ASP-DAC 2009: 793-798
182		Michiko Inoue, Tsuyoshi Suzuki, Hideo Fujiwara: Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms. DISC 2009: 172-173
181		Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara: Partial Scan Approach for Secret Information Protection. European Test Symposium 2009: 143-148
180		Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara: RTL DFT techniques to enhance defect coverage for functional test sequences. HLDVT 2009: 160-165
179		Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara: A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification. VTS 2009: 71-76
	2008
178		Yu Hu, Xiang Fu, Xiaoxin Fan, Hideo Fujiwara: Localized random access scan: Towards low area and routing overhead. ASP-DAC 2008: 565-570
177		Tomokazu Yoneda, Hideo Fujiwara: Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. DATE 2008: 1366-1369
176		Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, Hideo Fujiwara: A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 999-1012 (2008)
175		Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi: A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1535-1544 (2008)
174		Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara: Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips. IEICE Transactions 91-D(10): 2440-2448 (2008)
173		Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara: Scheduling Power-Constrained Tests through the SoC Functional Bus. IEICE Transactions 91-D(3): 736-746 (2008)
172		Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara: Test Scheduling for Multi-Clock Domain SoCs under Power Constraint. IEICE Transactions 91-D(3): 747-755 (2008)
171		Masato Nakasato, Michiko Inoue, Satoshi Ohtake, Hideo Fujiwara: Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors. IEICE Transactions 91-D(3): 763-770 (2008)
170		Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara: Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints. IEICE Transactions 91-D(3): 807-814 (2008)
169		Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara: On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time. IEICE Transactions 91-D(7): 1999-2007 (2008)
168		Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara: NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints. IEICE Transactions 91-D(7): 2008-2017 (2008)
	2007
167		Dan Zhao, Unni Chandran, Hideo Fujiwara: Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores. ASP-DAC 2007: 714-719
166		Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara: Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. ASP-DAC 2007: 720-725
165		Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara: A DFT Method for Time Expansion Model at Register Transfer Level. DAC 2007: 682-687
164		Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara: Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. DATE 2007: 231-236
163		Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara: Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. European Test Symposium 2007: 35-42
162		Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara: Efficient path delay test generation based on stuck-at test generation using checker circuitry. ICCAD 2007: 418-423
161		Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara: Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing. ISCAS 2007: 2942-2945
160		Dong Xiang, Yang Zhao, Kaiwei Li, Hideo Fujiwara: Fast and effective fault simulation for path delay faults based on selected testable paths. ITC 2007: 1-10
159		Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara: Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. VTS 2007: 369-374
158		Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara: TAM Design and Optimization for Transparency-Based SoC Test. VTS 2007: 381-388
157		Dong Xiang, Mingjing Chen, Hideo Fujiwara: Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. IEEE Trans. Computers 56(12): 1619-1628 (2007)
156		Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara: Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction. IEEE Trans. Computers 56(4): 557-562 (2007)
155		Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara: Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. IEEE Trans. VLSI Syst. 15(7): 790-800 (2007)
154		Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara: Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. IEICE Transactions 90-D(1): 296-305 (2007)
153		Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara: Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tauk-Notation. IEICE Transactions 90-D(8): 1202-1212 (2007)
152		Ilia Polian, Hideo Fujiwara: Functional Constraints vs. Test Compression in Scan-Based Delay Testing. J. Electronic Testing 23(5): 445-455 (2007)
	2006
151		Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara: A memory grouping method for sharing memory BIST logic. ASP-DAC 2006: 671-676
150		Ilia Polian, Hideo Fujiwara: Functional constraints vs. test compression in scan-based delay testing. DATE 2006: 1039-1044
149		Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara: Power-constrained test scheduling for multi-clock domain SoCs. DATE 2006: 297-302
148		Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell: Electrical Behavior of GOS Fault affected Domino Logic Cell. DELTA 2006: 183-189
147		Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara: Low-Cost Hardening of Image Processing Applications Against Soft Errors. DFT 2006: 274-279
146		Chia Yee Ooi, Hideo Fujiwara: A New Class of Sequential Circuits with Acyclic Test Generation Complexity. ICCD 2006
145		Dong Xiang, Kaiwei Li, Hideo Fujiwara, Jiaguang Sun: Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests. ICCD 2006
144		Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara: Power-Constrained SOC Test Schedules through Utilization of Functional Buses. ICCD 2006
143		Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara: A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits. VLSI-SoC 2006: 308-313
142		Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara: BIST Pretest of ICs: Risks and Benefits. VTS 2006: 142-149
141		Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. IEEE Trans. VLSI Syst. 14(11): 1203-1215 (2006)
140		Erik Larsson, Hideo Fujiwara: System-on-chip test scheduling with reconfigurable core wrappers. IEEE Trans. VLSI Syst. 14(3): 305-309 (2006)
139		Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara: Effect of BIST Pretest on IC Defect Level. IEICE Transactions 89-D(10): 2626-2636 (2006)
138		Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara: Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch. IEICE Transactions 89-D(3): 1165-1172 (2006)
137		Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara: A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips. IEICE Transactions 89-D(4): 1490-1497 (2006)
136		Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara: A Low Power Deterministic Test Using Scan Chain Disable Technique. IEICE Transactions 89-D(6): 1931-1939 (2006)
135		Tomokazu Yoneda, Hideo Fujiwara: Design for consecutive transparency method of RTL circuits. Systems and Computers in Japan 37(2): 1-10 (2006)
	2005
134		Dong Xiang, Ming-Jing Chen, Hideo Fujiwara: Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST. Asian Test Symposium 2005: 126-131
133		Tomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara: Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability. Asian Test Symposium 2005: 150-155
132		Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara: Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. Asian Test Symposium 2005: 254-259
131		Thomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja: A Class of Linear Space Compactors for Enhanced Diagnostic. Asian Test Symposium 2005: 260-265
130		Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara: An Effective Design for Hierarchical Test Generation Based on Strong Testability. Asian Test Symposium 2005: 288-293
129		Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara: A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. Asian Test Symposium 2005: 306-311
128		Dong Xiang, Kaiwei Li, Hideo Fujiwara: Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops. Asian Test Symposium 2005: 318-323
127		Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki: Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. Asian Test Symposium 2005: 444-449
126		Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Testing Superscalar Processors in Functional Mode. FPL 2005: 747-750
125		Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Instruction-based delay fault self-testing of pipelined processor cores. ISCAS (6) 2005: 5686-5689
124		Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, Hideo Fujiwara: Design and analysis of multiple weight linear compactors of responses containing unknown values. ITC 2005: 10
123		Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara: Improving test effectiveness of scan-based BIST by scan chain partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 916-927 (2005)
122		Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara: Classification of Sequential Circuits Based on tauk Notation and Its Applications. IEICE Transactions 88-D(12): 2738-2747 (2005)
121		Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Delay Fault Testing of Processor Cores in Functional Mode. IEICE Transactions 88-D(3): 610-618 (2005)
120		Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara: Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST. IEICE Transactions 88-D(6): 1210-1216 (2005)
119		Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara: Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths. IEICE Transactions 88-D(8): 1940-1947 (2005)
	2004
118		Kazuko Kambe, Michiko Inoue, Hideo Fujiwara: Efficient Template Generation for Instruction-Based Self-Test of Processor Cores. Asian Test Symposium 2004: 152-157
117		Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara: Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths. Asian Test Symposium 2004: 32-39
116		Debesh Kumar Das, Tomoo Inoue, Susanta Chakraborty, Hideo Fujiwara: Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity. Asian Test Symposium 2004: 342-347
115		Chia Yee Ooi, Hideo Fujiwara: Classification of Sequential Circuits Based on ?k Notation. Asian Test Symposium 2004: 348-353
114		Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Instruction-Based Delay Fault Self-Testing of Processor Cores. VLSI Design 2004: 933-
113		Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian: Design & Test Education in Asia. IEEE Design & Test of Computers 21(4): 331-338 (2004)
112		Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng: Efficient test solutions for core-based designs. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 758-775 (2004)
111		Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara: A DFT Selection Method for Reducing Test Application Time of System-on-Chips. IEICE Transactions 87-D(3): 609-619 (2004)
110		Erik Larsson, Hideo Fujiwara: Preemptive System-on-Chip Test Scheduling. IEICE Transactions 87-D(3): 620-629 (2004)
109		Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara: New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. J. Electronic Testing 20(3): 315-323 (2004)
	2003
108		Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara: Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning. Asian Test Symposium 2003: 12-17
107		Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara: A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. Asian Test Symposium 2003: 130-135
106		Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara: Test Synthesis for Datapaths Using Datapath-Controller Functions. Asian Test Symposium 2003: 294-299
105		Dong Xiang, Shan Gu, Hideo Fujiwara: Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis. Asian Test Symposium 2003: 300-305
104		Erik Larsson, Hideo Fujiwara: Optimal System-on-Chip Test Scheduling. Asian Test Symposium 2003: 306-311
103		Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara: A DFT Selection Method for Reducing Test Application Time of System-on-Chips. Asian Test Symposium 2003: 412-417
102		Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara: Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models. Asian Test Symposium 2003: 58-63
101		Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Software-Based Delay Fault Testing of Processor Cores. Asian Test Symposium 2003: 68-71
100		Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara: A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms. DATE 2003: 10310-10315
99		Tomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara: Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability. ITC 2003: 415-422
98		Tomokazu Yoneda, Hideo Fujiwara: Design for Consecutive Transparency of Cores in System-on-a-Chip. VTS 2003: 287-292
97		Erik Larsson, Hideo Fujiwara: Test Resource Partitioning and Optimization for SOC Designs. VTS 2003: 319-324
96		Dong Xiang, Yi Xu, Hideo Fujiwara: Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution. IEEE Trans. Computers 52(8): 1063-1075 (2003)
	2002
95		Tomoo Inoue, Tomokazu Miura, Akio Tamura, Hideo Fujiwara: A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design. Asian Test Symposium 2002: 128-133
94		Emil Gizdarski, Hideo Fujiwara: Fault Set Partition for Efficient Width Compression. Asian Test Symposium 2002: 194-199
93		Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng: Integrated Test Scheduling, Test Parallelization and TAMDesign. Asian Test Symposium 2002: 397-404
92		Atlaf Ul Amin, Satoshi Ohtake, Hideo Fujiwara: Design for Two-Pattern Testability of Controller-Data Path Circuits. Asian Test Symposium 2002: 73-79
91		Dong Xiang, Shan Gu, Hideo Fujiwara: Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis. Asian Test Symposium 2002: 86-
90		Michiko Inoue, Chikateru Jinno, Hideo Fujiwara: An Extended Class of Sequential Circuits with Combinational Test Generation Complexity. ICCD 2002: 200-205
89		Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa: A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits. VTS 2002: 321-327
88		Emil Gizdarski, Hideo Fujiwara: SPIRIT: a highly robust combinational test generation algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1446-1458 (2002)
87		Dong Xiang, Hideo Fujiwara: Handling the pin overhead problem of DFTs for high-quality and at-speed tests. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1105-1113 (2002)
86		Michiko Inoue, Emil Gizdarski, Hideo Fujiwara: Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. J. Electronic Testing 18(1): 55-62 (2002)
85		Tomokazu Yoneda, Hideo Fujiwara: Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores. J. Electronic Testing 18(4-5): 487-501 (2002)
84		Yoshiaki Katayama, Eiichiro Ueda, Hideo Fujiwara, Toshimitsu Masuzawa: A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings. J. Parallel Distrib. Comput. 62(5): 865-884 (2002)
83		Toshinori Hosokawa, Tomoo Inoue, Toshihiro Hiraoka, Hideo Fujiwara: Test sequence compaction methods for acyclic sequential circuits using a time expansion model. Systems and Computers in Japan 33(10): 105-115 (2002)
82		Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: Parallel algorithms for selection on the BSP and BSP* models. Systems and Computers in Japan 33(12): 97-107 (2002)
81		Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A layout adjustment problem for disjoint rectangles preserving orthogonal order. Systems and Computers in Japan 33(2): 31-42 (2002)
80		Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara: A nonscan DFT method for controllers to provide complete fault efficiency. Systems and Computers in Japan 33(5): 64-75 (2002)
	2001
79		Satoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara: A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability. ASP-DAC 2001: 331-334
78		Md. Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara: Design for Hierarchical Two-Pattern Testability of Data Paths. Asian Test Symposium 2001: 11-16
77		Tomokazu Yoneda, Hideo Fujiwara: A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability. Asian Test Symposium 2001: 193-198
76		Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara: BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths. Asian Test Symposium 2001: 313-318
75		Emil Gizdarski, Hideo Fujiwara: A Framework for Low Complexity Static Learning. DAC 2001: 546-549
74		Michiko Inoue, Shinya Umetani, Toshimitsu Masuzawa, Hideo Fujiwara: Adaptive Long-Lived O(k2)-Renaming with O(k2) Steps. DISC 2001: 123-135
73		Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara: Testable Design of Sequential Circuits with Improved Fault Efficiency. VLSI Design 2001: 128-133
72		Emil Gizdarski, Hideo Fujiwara: SPIRIT: A Highly Robust Combinational Test Generation Algorithm. VTS 2001: 346-351
71		Chikara Ohori, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A causal broadcast protocol for distributed mobile systems. Systems and Computers in Japan 32(3): 65-75 (2001)
	2000
70		Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara: A non-scan DFT method at register-transfer level to achieve complete fault efficiency. ASP-DAC 2000: 599-604
69		Emil Gizdarski, Hideo Fujiwara: Spirit: satisfiability problem implementation for redundancy identification and test generation. Asian Test Symposium 2000: 171-178
68		Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara: Single-control testability of RTL data paths for BIST. Asian Test Symposium 2000: 210-215
67		Xiaowei Li, Toshimitsu Masuzawa, Hideo Fujiwara: Strong self-testability for data paths high-level synthesis. Asian Test Symposium 2000: 229-234
66		Michiko Inoue, Emil Gizdarski, Hideo Fujiwara: A class of sequential circuits with combinational test generation complexity under single-fault assumption. Asian Test Symposium 2000: 398-403
65		Tomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara: Test Generation for Acyclic Sequential Circuits with Hold Registers. ICCAD 2000: 550-556
64		Dong Xiang, Yi Xu, Hideo Fujiwara: Non-scan design for testability for synchronous sequential circuits based on conflict analysis. ITC 2000: 520-529
63		Hideo Fujiwara: A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity. VLSI Design 2000: 288-293
62		Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara: Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency. VLSI Design 2000: 300-305
61		Hideo Fujiwara: A New Class of Sequential Circuits with Combinational Test Generation Complexity. IEEE Trans. Computers 49(9): 895-905 (2000)
60		Xiaowei Li, Paul Y. S. Cheung, Hideo Fujiwara: LFSR-Based Deterministic TPG for Two-Pattern Testing. J. Electronic Testing 16(5): 419-426 (2000)
59		Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara: A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency. J. Electronic Testing 16(5): 553-566 (2000)
	1999
58		Toshinori Hosokawa, Toshihiro Hiraoka, Tomoo Inoue, Hideo Fujiwara: Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model. Asian Test Symposium 1999: 192-
57		Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara: New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. Asian Test Symposium 1999: 263-268
56		Tomoya Takasaki, Hideo Fujiwara, Tomoo Inoue: A High-Level Synthesis Approach to Partial Scan Design Based on Acyclic Structure. Asian Test Symposium 1999: 309-314
55		Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara: A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. Asian Test Symposium 1999: 5-12
54		Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: Parallel Algorithms for All Nearest Neighbors of Binary Images on the BSP Model. ISPAN 1999: 394-399
53		Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A cost optimal parallel algorithm for weighted distance transforms. Parallel Computing 25(4): 405-416 (1999)
	1998
52		Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara: Partial Scan Design Methods Based on Internally Balanced Structure. ASP-DAC 1998: 211-216
51		Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara: An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits. Asian Test Symposium 1998: 190-197
50		Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara: A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency. Asian Test Symposium 1998: 204-211
49		Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa, Hideo Fujiwara: A High-Level Synthesis Method for Weakly Testable Data Paths. Asian Test Symposium 1998: 40-45
48		Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A Layout Adjustment Problem for Disjoint Rectangles Preserving Orthogonal Order. Graph Drawing 1998: 183-197
47		Sen Moriya, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: SelfStabilizing WaitFree Clock Synchronization with Bounded Space. OPODIS 1998: 129-144
46		Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara: Universal Fault Diagnosis for Lookup Table FPGAs. IEEE Design & Test of Computers 15(1): 39-44 (1998)
45		Hideo Fujiwara: Needed: Third-generation ATPG Benchmarks. IEEE Design & Test of Computers 15(1): 96- (1998)
44		Michiko Inoue, Hideo Fujiwara: An approach to test synthesis from higher level. Integration 26(1-2): 101-116 (1998)
43		Hiroshi Youra, Tomoo Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: On the synthesis of synchronizable finite state machines with partial scan. Systems and Computers in Japan 29(1): 53-62 (1998)
42		Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara: Partial scan design methods based on internally balanced structure. Systems and Computers in Japan 29(10): 26-35 (1998)
	1997
41		Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara: Testing for the programming circuit of LUT-based FPGAs. Asian Test Symposium 1997: 242-247
40		Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara: On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs. Asian Test Symposium 1997: 276-281
39		Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara: Sequential Test Generation Based on Circuit Pseudo-Transformation. Asian Test Symposium 1997: 62-67
38		Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A Parallel Algorithm for Weighted Distance Transforms. IPPS 1997: 407-412
37		Michiko Inoue, Sen Moriya, Toshimitsu Masuzawa, Hideo Fujiwara: Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System. WDAG 1997: 290-304
36		Eiichiro Ueda, Yoshiaki Katayama, Toshimitsu Masuzawa, Hideo Fujiwara: A latency-optimal superstabilizing mutual exclusion protocol. WSS 1997: 110-124
35		Akihiro Fujiwara, Toshimitsu Masuzawa, Hideo Fujiwara: Parallel algorithms for connected-component problems of gray-scale images. Systems and Computers in Japan 28(1): 74-86 (1997)
34		Katsuyuki Takabatake, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: Non-scan design for testable data paths using thru operation. Systems and Computers in Japan 28(10): 60-68 (1997)
33		Hideo Fujiwara, Satoshi Ohtake, Tomoya Takasaki: A sequential circuit structure with combinational test generation complexity and its application. Systems and Computers in Japan 28(11): 11-21 (1997)
32		Daisuke Yoshida, Toshimitsu Masuzawa, Hideo Fujiwara: Fault-tolerant distributed algorithms for autonomous mobile robots with crash faults. Systems and Computers in Japan 28(2): 33-43 (1997)
	1996
31		Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara: An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan. Asian Test Symposium 1996: 130-135
30		Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara: A Test Methodology for Interconnect Structures of LUT-based FPGAs. Asian Test Symposium 1996: 68-74
29		Yasuo Sato, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A Snapshot Algorithm for Distributed Mobile Systems. ICDCS 1996: 734-743
	1995
28		Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto: Universal test complexity of field-programmable gate arrays. Asian Test Symposium 1995: 259-265
27		Tomoo Inoue, Hironori Maeda, Hideo Fujiwara: A scheduling problem in test generation. VTS 1995: 344-349
26		Hideo Fujiwara, Tomoo Inoue: Optimal Granularity and Scheme of Parallel Test Generation in a Distributed System. IEEE Trans. Parallel Distrib. Syst. 6(7): 677-686 (1995)
25		Hideo Fujiwara: Foreword. IEICE Transactions 78-D(7): 789-790 (1995)
24		Akihiro Fujiwara, Toshimitsu Masuzawa, Hideo Fujiwara: An Optimal Parallel Algorithm for the Euclidean Distance Maps of 2-D Binary Images. Inf. Process. Lett. 54(5): 295-300 (1995)
	1993
23		Hideo Fujiwara, Akihiro Yamamoto: Parity-scan design to reduce the cost of test application. IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1604-1611 (1993)
	1992
22		Takayuli Fujino, Hideo Fujiwara: An Efficient Test Generation Algorithm Based on Search State Dominance. FTCS 1992: 246-253
21		Hideo Fujiwara, Akihiro Yamamoto: Parity-Scan Design to Reduce the Cost of Test Application. ITC 1992: 283-292
	1990
20		Hideo Fujiwara: Three-valued neural networks for test generation. FTCS 1990: 64-71
19		Hideo Fujiwara: Computational Complexity of Controllability/Observability Problems for Combinational Circuits. IEEE Trans. Computers 39(6): 762-767 (1990)
18		Hideo Fujiwara, Tomoo Inoue: Optimal granularity of test generation in a distributed system. IEEE Trans. on CAD of Integrated Circuits and Systems 9(8): 885-892 (1990)
	1989
17		Hideo Fujiwara: Enhancing random-pattern coverage of programmable logic arrays via masking technique. IEEE Trans. on CAD of Integrated Circuits and Systems 8(9): 1022-1025 (1989)
	1988
16		Hideo Fujiwara: Computational complexity of controllability/observability problems for combinational circuits. FTCS 1988: 64-69
15		Hideo Fujiwara, Osamu Fujisawa, Kazunori Hikone: Enhancing Random-Pattern Coverage of Programmable Logic Arrays via Masking Technique. ITC 1988: 642-648
	1987
14		Robert P. Treuer, Vinod K. Agarwal, Hideo Fujiwara: A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead. IEEE Trans. Computers 36(3): 369-373 (1987)
	1985
13		Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita: A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead. ITC 1985: 574-582
	1984
12		Hideo Fujiwara: A New PLA Design for Universal Testability. IEEE Trans. Computers 33(8): 745-750 (1984)
	1983
11		Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara: Test generation for scan design circuits with tri-state modules and bidirectional terminals. DAC 1983: 71-78
10		Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara: An Easily Testable Design of Programmable Logic Arrays for Multiple Faults. IEEE Trans. Computers 32(11): 1038-1046 (1983)
9		Hideo Fujiwara, Takeshi Shimono: On the Acceleration of Test Generation Algorithms. IEEE Trans. Computers 32(12): 1137-1144 (1983)
	1982
8		Hideo Fujiwara, Shunichi Toida: The Complexity of Fault Detection Problems for Combinational Logic Circuits. IEEE Trans. Computers 31(6): 555-560 (1982)
	1981
7		Hideo Fujiwara, Kozo Kinoshita: A Design of Programmable Logic Arrays with Universal Tests. IEEE Trans. Computers 30(11): 823-828 (1981)
6		Hideo Fujiwara: On Closedness and Test Complexity of Logic Circuits. IEEE Trans. Computers 30(8): 556-562 (1981)
	1978
5		Shunichiro Nakamura, Shinichi Murai, Chiyoji Tanaka, Masayuki Terai, Hideo Fujiwara, Kozo Kinoshita: LORES - Logic Reorganization System. DAC 1978: 250-260
4		Hideo Fujiwara, Kozo Kinoshita: On the Computational Complexity of System Diagnosis. IEEE Trans. Computers 27(10): 881-885 (1978)
3		Hideo Fujiwara, Kozo Kinoshita: Connection Assignments for Probabilistically Diagnosable Systems. IEEE Trans. Computers 27(3): 280-283 (1978)
2		Hideo Fujiwara, Kozo Kinoshita: Some Existence Theorems for Probabilistically Diagnosable Systems. IEEE Trans. Computers 27(4): 379-384 (1978)
	1975
1		Hideo Fujiwara, Yoich Nagao, Tsutomu Sasao, Kozo Kinoshita: Easily Testable Sequential Machines with Extra Inputs. IEEE Trans. Computers 24(8): 821-826 (1975)

Coauthor Index

1	Raghavendra Adiga	[190]
2	Vinod K. Agarwal	[14]
3	Md. Altaf-Ul-Amin	[78]
4	Atlaf Ul Amin	[92]
5	Gandhi Arpit	[190]
6	Klas Arvidsson	[93] [112]
7	Bernd Becker	[147]
8	Bhargab B. Bhattacharya	[73]
9	Krishnendu Chakrabarty	[174] [176] [180] [183] [185] [191]
10	Susanta Chakraborty	[116]
11	Unni Chandran	[167]
12	Ming-Jing Chen	[108] [123] [134]
13	Mingjing Chen	[157]
14	Paul Y. S. Cheung	[60]
15	Thomas Clouqueur	[122] [124] [131] [138] [153] [155]
16	Mariane Comte	[148]
17	Debesh Kumar Das (Debesh K. Das)	[57] [65] [73] [109] [113] [116]
18	Hiroshi Date	[103] [107] [111]
19	Xiaoxin Fan	[178]
20	Hongxia Fang	[180] [185]
21	Xiang Fu	[178]
22	Takayuli Fujino	[22]
23	Osamu Fujisawa	[15]
24	Akihiro Fujiwara	[24] [35] [38] [53] [54] [82]
25	Katsuya Fujiwara	[198] [206] [212]
26	Emil Gizdarski	[66] [69] [72] [75] [86] [88] [94]
27	Shan Gu	[91] [105]
28	Muneo Hasegawa	[181] [205]
29	Kunihiko Hayashi	[48] [81]
30	Takeshi Higashimura	[49]
31	Kazunori Hikone	[15]
32	Toshihiro Hiraoka	[58] [83]
33	Keigo Hori	[208]
34	Toshinori Hosokawa	[51] [58] [83] [103] [107] [111] [130] [188]
35	Yu Hu	[178]
36	Jiedi Huang	[199]
37	Ronghua Huang	[161]
38	Fawnizu Azmadi Hussin	[144] [163] [166] [168] [169] [173]
39	Hideyuki Ichihara	[130] [158] [187]
40	Masahiro Imanishi	[164]
41	Michiko Inoue	[29] [34] [37] [38] [44] [47] [48] [49] [53] [54] [55] [66] [71] [74] [81] [82] [86] [90] [101] [106] [114] [117] [118] [119] [121] [125] [126] [127] [132] [136] [141] [171] [181] [182] [189] [193] [194] [199] [200] [201] [205] [208] [209]
42	Ryoichi Inoue	[188]
43	Tomoo Inoue	[18] [26] [27] [28] [30] [31] [39] [40] [41] [42] [43] [46] [51] [52] [56] [58] [65] [83] [95] [116] [130] [158] [179] [184] [187]
44	Takashi Ishimizu	[54] [82]
45	Tsuyoshi Iwagaki	[102] [127] [136] [143] [162]
46	Hiroshi Iwata	[186] [194] [196] [197] [201]
47	Hiroyuki Iwata	[129] [165] [175]
48	Minoru Izutsu	[68]
49	Maksim Jenihhin	[211]
50	Chikateru Jinno	[90]
51	Seiji Kajihara	[193]
52	Kazuko Kambe	[118] [127]
53	Mineo Kaneko	[162]
54	Yoshiaki Katayama	[36] [84]
55	Kozo Kinoshita	[1] [2] [3] [4] [5] [7] [10] [11] [13]
56	Jishun Kuang	[199]
57	Erik Larsson	[93] [97] [104] [110] [112] [140] [195] [203]
58	Kaiwei Li	[128] [145] [156] [160]
59	Xiaowei Li	[60] [67]
60	Yungang Li	[113]
61	Hironori Maeda	[27]
62	Kimihiko Masuda	[149] [172]
63	Toshimitsu Masuzawa	[24] [29] [31] [32] [34] [35] [36] [37] [38] [43] [47] [48] [49] [50] [53] [54] [59] [62] [67] [68] [70] [71] [74] [76] [80] [81] [82] [84]
64	Hiroyuki Michinishi	[28] [30] [41]
65	Takahiro Mihara	[51] [65]
66	Yinghua Min	[113]
67	Tomokazu Miura	[95]
68	Shunjiro Miwa	[89]
69	Masahide Miyazaki	[103] [107] [111] [137] [151]
70	Satoshi Miyazaki	[40] [46]
71	Sen Moriya	[37] [47]
72	Shinichi Murai	[5] [11]
73	Michiaki Muraoka	[103] [107] [111]
74	Shintaro Nagai	[79]
75	Yoich Nagao	[1]
76	Shunichiro Nakamura	[5]
77	Yoshiyuki Nakamura	[120] [138] [139] [142] [155]
78	Makoto Nakao	[209]
79	Masato Nakasato	[147] [154] [171]
80	Kenji Noda	[49]
81	Marie Engelene J. Obien	[192] [198] [202] [207] [210]
82	Takuji Ogihara	[11]
83	Chikara Ohori	[71]
84	Satoshi Ohtake	[33] [39] [50] [55] [57] [59] [70] [73] [78] [79] [80] [89] [92] [100] [102] [109] [129] [132] [143] [147] [148] [154] [162] [171] [179] [184] [186] [192] [196] [197] [201] [207] [210]
85	Kouhei Ohtani	[100]
86	Hiroyuki Okamoto	[106]
87	Naoki Okamoto	[130]
88	Takuji Okamoto	[28] [30] [41]
89	Chia Yee Ooi	[115] [122] [146] [153] [175] [204]
90	Alex Orailoglu	[144] [166] [173]
91	Zebo Peng	[93] [112]
92	Ilia Polian	[147] [150] [152]
93	Jaan Raik	[211]
94	Anna Rannaste	[211]
95	Michel Renovell	[148]
96	Kewal K. Saluja	[10] [13] [62] [101] [114] [121] [124] [125] [126] [131] [138] [141] [154] [155] [190]
97	Chiiho Sano	[65]
98	Alodeep Sanyal	[191]
99	Tsutomu Sasao	[1]
100	Yasuo Sato	[29] [189] [193] [209]
101	Jacob Savir	[117] [119] [120] [139] [142]
102	Takeshi Shimono	[9]
103	Akiko Shuto	[158] [187]
104	Adit D. Singh	[190]
105	Virendra Singh	[101] [114] [121] [125] [126] [141] [190] [195] [203]
106	Jia-Guang Sun (Jiaguang Sun)	[108] [123] [145] [156]
107	Kazuhiro Suzuki	[106]
108	Tsuyoshi Suzuki	[182]
109	Katsuyuki Takabatake	[34]
110	Hisakazu Takakuwa	[133]
111	Yuzo Takamatsu	[11]
112	Tomoya Takasaki	[33] [42] [52] [56]
113	Akira Taketani	[194] [200]
114	Hideo Tamamoto	[198] [206] [212]
115	Akio Tamura	[95]
116	Chiyoji Tanaka	[5]
117	Masayuki Terai	[5]
118	Shunichi Toida	[8]
119	Robert P. Treuer	[14]
120	Jaynarayan T. Tudu	[195] [203]
121	Raimund Ubar	[211]
122	Tetsuo Uchiyama	[99]
123	Eiichiro Ueda	[36] [84]
124	Shinya Umetani	[74]
125	Taavi Viilukas	[211]
126	Hiroki Wada	[62] [68] [70] [76] [79]
127	Dong Xiang	[64] [87] [91] [96] [105] [108] [123] [128] [134] [145] [156] [157] [160] [176]
128	Shiyi Xu	[113]
129	Yi Xu	[64] [96]
130	Ken-ichi Yamaguchi	[76] [117] [119]
131	Akihiro Yamamoto	[21] [23]
132	Hyunbean Yi	[193]
133	Mahmut Yilmaz	[191]
134	Tokumi Yokohira	[28] [30] [41]
135	Tomokazu Yoneda	[77] [85] [98] [99] [129] [133] [135] [137] [144] [149] [151] [158] [159] [161] [163] [164] [165] [166] [168] [169] [170] [172] [173] [174] [175] [177] [181] [183] [187] [189] [193] [194] [200] [205] [208] [209]
136	Daisuke Yoshida	[32]
137	Yuki Yoshikawa	[132] [179] [184]
138	Zhiqiang You	[117] [119] [136] [199]
139	Hiroshi Youra	[31] [43]
140	Thomas Edison Yu	[159] [170] [174] [183]
141	Kamran Zarrineh	[124]
142	Dan Zhao	[161] [167]
143	Danella Zhao	[159] [170]
144	Yang Zhao	[160] [176]
145	Yervant Zorian	[113]

Colors in the list of coauthors

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