Hidehiro Fujiwara

	2012
18		Yasumasa Tsukamoto, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Changhwan Shin, Tsu-Jae King Liu: Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application. ISQED 2012: 270-274
17		Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki: A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. ISSCC 2012: 236-238
16		Takashi Matsuda, Shintaro Izumi, Yasuharu Sakai, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto: Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes. IEICE Transactions 95-B(1): 178-188 (2012)
15		Shunsuke Okumura, Hidehiro Fujiwara, Kosuke Yamaguchi, Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi: A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme. IEICE Transactions 95-C(4): 579-585 (2012)
	2011
14		Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Shigeki Tawa, Koji Maekawa, Motoshige Igarashi, Koji Nii: A dynamic body-biased SRAM with asymmetric halo implant MOSFETs. ISLPED 2011: 285-290
13		Yuichiro Ishii, Hidehiro Fujiwara, Shinji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yuji Kihara, K. Yanagisawa: A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues. J. Solid-State Circuits 46(11): 2535-2544 (2011)
	2010
12		Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto: Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. SoCC 2010: 519-524
	2009
11		Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. ISQED 2009: 659-663
10		Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. VLSI Design 2009: 295-300
9		Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A Dependable SRAM with 7T/14T Memory Cells. IEICE Transactions 92-C(4): 423-432 (2009)
	2008
8		Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: Quality of a Bit (QoB): A New Concept in Dependable SRAM. ISQED 2008: 98-102
7		Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. IEEE Trans. VLSI Syst. 16(6): 620-627 (2008)
6		Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. IEICE Transactions 91-C(4): 543-552 (2008)
	2007
5		Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. ISVLSI 2007: 107-112
4		Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme. IEICE Transactions 90-A(12): 2695-2702 (2007)
3		Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes. IEICE Transactions 90-C(10): 1949-1956 (2007)
	2006
2		Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ISLPED 2006: 61-66
1		Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. IEICE Transactions 89-A(12): 3634-3641 (2006)

Coauthor Index

1	Kazutami Arimoto	[12]
2	Motoshige Igarashi	[14]
3	Yusuke Iguchi	[3] [4] [5] [6] [8] [9] [10] [11]
4	Kazuya Ishihara	[12]
5	Yuichiro Ishii	[13] [17]
6	Shintaro Izumi	[16]
7	Hiroshi Kawaguchi	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [15] [16]
8	Hiroyuki Kawai	[12]
9	Kentaro Kawakami	[1]
10	Yuji Kihara	[13]
11	Tsu-Jae King Liu	[18]
12	Koji Maekawa	[14]
13	Takashi Matsuda	[16]
14	Shinji Mikami	[1]
15	Junichi Miyakoshi	[1] [2] [7]
16	Yasuhiro Morita	[1] [2] [3] [4] [5] [6] [7] [8]
17	Yuichiro Murachi	[2] [7]
18	Hirofumi Nakano	[12]
19	Koji Nii	[1] [2] [3] [4] [5] [6] [7] [11] [12] [13] [14] [17] [18]
20	Hiroki Noguchi	[1] [3] [4] [5] [6] [7] [8] [9] [10] [11]
21	Chikara Ohta	[16]
22	Shunsuke Okumura	[6] [8] [9] [10] [11] [15]
23	Yasuharu Sakai	[16]
24	Yasuhisa Shimazaki	[17]
25	Changhwan Shin	[18]
26	Takashi Takeuchi	[16]
27	Koji Tanaka	[17]
28	Shinji Tanaka	[13] [17]
29	Shigeki Tawa	[14]
30	Yasumasa Tsukamoto	[13] [14] [17] [18]
31	Makoto Yabuuchi	[12] [14] [17] [18]
32	Kosuke Yamaguchi	[15]
33	K. Yanagisawa	[13]
34	Masahiko Yoshimoto	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [15] [16]
35	Shusuke Yoshimoto	[11] [15]

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