Eiji Fujiwara

	2010
40		Kazuyoshi Suzuki, Eiji Fujiwara: MacWilliams Identity for M-Spotty Weight Enumerator. IEICE Transactions 93-A(2): 526-531 (2010)
	2009
39		Haruhiko Kaneko, Eiji Fujiwara: A Class of Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols. IEICE Transactions 92-A(6): 1508-1519 (2009)
38		Haruhiko Kaneko, Eiji Fujiwara: M-Ary Substitution/Deletion/Insertion/Adjacent-Symbol-Transposition Error Correcting Codes for Data Entry Systems. IEICE Transactions 92-A(7): 1668-1676 (2009)
37		Haruhiko Kaneko, Eiji Fujiwara: Joint source-cryptographic-channel coding for dependable systems. IJCAT 34(4): 249-256 (2009)
	2008
36		Haruhiko Kaneko, Takuya Matsuzaka, Eiji Fujiwara: Three-Level Error Control Coding for Dependable Solid-State Drives. PRDC 2008: 281-288
	2007
35		Haruhiko Kaneko, Eiji Fujiwara: Joint Source-Cryptographic-Channel Coding Based on Linear Block Codes. AAECC 2007: 158-167
34		Haruhiko Kaneko, Eiji Fujiwara: Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks. DFT 2007: 349-358
33		Kazuyoshi Suzuki, Toshihiko Kashiyama, Eiji Fujiwara: A General Class of M-Spotty Byte Error Control Codes. IEICE Transactions 90-A(7): 1418-1427 (2007)
32		Kazuteru Namba, Eiji Fujiwara: Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings. Systems and Computers in Japan 38(8): 54-60 (2007)
	2006
31		Hiroyuki Ohde, Haruhiko Kaneko, Eiji Fujiwara: Low-Density Triple-Erasure Correcting Codes for Dependable Distributed Storage Systems. DFT 2006: 175-183
30		Kazuyoshi Suzuki, Toshihiko Kashiyama, Eiji Fujiwara: Complex M-Spotty Byte Error Control Codes. IEICE Transactions 89-A(9): 2396-2404 (2006)
	2005
29		Jien-Chung Lo, Yu-Lun Wan, Eiji Fujiwara: Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes. DFT 2005: 120-130
28		Ganesan Umanesan, Eiji Fujiwara: Parallel Decoding Cyclic Burst Error Correcting Codes. IEEE Trans. Computers 54(1): 87-92 (2005)
	2004
27		Haruhiko Kaneko, Mariko Numakami, Eiji Fujiwara: Nonsystematic M-Ary Asymmetric Error Correcting Codes Designed by Multilevel Coding Method. PRDC 2004: 219-226
26		Haruhiko Kaneko, Eiji Fujiwara: A Class of M-Ary Asymmetric Symbol Error Correcting Codes for Data Entry Devices. IEEE Trans. Computers 53(2): 159-167 (2004)
	2003
25		Haruhiko Kaneko, Eiji Fujiwara: Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols. DFT 2003: 242-249
24		Ganesan Umanesan, Eiji Fujiwara: A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes. IEEE Trans. Computers 52(7): 835-847 (2003)
	2002
23		Ganesan Umanesan, Eiji Fujiwara: A Class of Random Multiple Bits in a Byte Error Correcting (S t/b EC)Codes for Semiconductor Memory Systems. PRDC 2002: 247-256
	2001
22		Kazuteru Namba, Eiji Fujiwara: Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities. DFT 2001: 299-307
21		Kazuteru Namba, Eiji Fujiwara: A class of systematic m-ary single-symbol error correcting codes. Systems and Computers in Japan 32(6): 21-28 (2001)
	2000
20		Masato Kitakami, Hongyuan Chen, Eiji Fujiwara: Evaluations of Burst Error Recovery for VF Arithmetic Coding. DFT 2000: 183-191
19		Ganesan Umanesan, Eiji Fujiwara: Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems. DFT 2000: 192-200
	1999
18		Kiattichai Saowapa, Haruhiko Kaneko, Eiji Fujiwara: Systematic Deletion/Insertion Error Correcting Codes with Random Error Correction Capability. DFT 1999: 284-292
	1998
17		Eiji Fujiwara, Tepparit Ritthongpitak, Masato Kitakami: Optimal Two-Level Unequal Error Control Codes for Computer Systems. IEEE Trans. Computers 47(12): 1313-1325 (1998)
	1997
16		Mitsuru Hamada, Eiji Fujiwara: A Class of Error Control Codes for Byte Organized Memory Systems —SbEC-(Sb+S)ED Codes—. IEEE Trans. Computers 46(1): 105-109 (1997)
	1996
15		Tepparit Ritthongpitak, Masato Kitakami, Eiji Fujiwara: Optimal Two-Level Unequal Error Control Codes for Computer Systems. FTCS 1996: 190-199
14		Jien-Chung Lo, Eiji Fujiwara: Probability to Achieve TSC Goal. IEEE Trans. Computers 45(4): 450-460 (1996)
	1995
13		Eiji Fujiwara, Masato Kitakami: A Class of Optimal Fixed-Byte Error Protection Codes for Computer Systems. FTCS 1995: 310-319
12		Eiji Fujiwara, Masaharu Tanaka: Defect-Tolerant WSI File Memory System Using Address Permutation for Spare Allocation. IEICE Transactions 78-D(2): 130-137 (1995)
	1994
11		Eiji Fujiwara, Masato Kitakami: A class of error-correcting codes for byte-organized memory systems. IEEE Transactions on Information Theory 40(6): 1857-1865 (1994)
	1993
10		Eiji Fujiwara, Masaharu Tanaka: A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare Allocation. DFT 1993: 183-190
9		Jien-Chung Lo, Eiji Fujiwara: A Probabilistic Measurement for Totally Self-Checking Circuits. DFT 1993: 263-270
8		Eiji Fujiwara, Masato Kitakami: A Class of Error Locating Codes for Byte-Organized Memory Systems. FTCS 1993: 110-119
	1992
7		Eiji Fujiwara, Mitsuru Hamada: Single b-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems. FTCS 1992: 494-501
	1990
6		Eiji Fujiwara, Dhiraj K. Pradhan: Error-Control Coding in Computers. IEEE Computer 23(7): 63-72 (1990)
	1989
5		Thammavarapu R. N. Rao, Eiji Fujiwara: Error-control coding for computer systems. Prentice Hall 1989: I-XVI, 1-524
	1988
4		Kazumitsu Matsuzawa, Eiji Fujiwara: Masking asymmetric line faults using semi-distance codes. FTCS 1988: 354-359
	1987
3		Eiji Fujiwara, Kohji Matsuoka: A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing. IEEE Trans. Computers 36(1): 86-93 (1987)
	1984
2		Eiji Fujiwara, Nobuo Mutoh, Kohji Matsuoka: A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing. IEEE Trans. Computers 33(6): 578-583 (1984)
	1982
1		Shigeo Kaneda, Eiji Fujiwara: Single Byte Error Correcting - Double Byte Error Detecting Codes for Memory Systems. IEEE Trans. Computers 31(7): 596-602 (1982)

Coauthor Index

1	Hongyuan Chen	[20]
2	Mitsuru Hamada	[7] [16]
3	Shigeo Kaneda	[1]
4	Haruhiko Kaneko	[18] [25] [26] [27] [31] [34] [35] [36] [37] [38] [39]
5	Toshihiko Kashiyama	[30] [33]
6	Masato Kitakami	[8] [11] [13] [15] [17] [20]
7	Jien-Chung Lo	[9] [14] [29]
8	Kohji Matsuoka	[2] [3]
9	Takuya Matsuzaka	[36]
10	Kazumitsu Matsuzawa	[4]
11	Nobuo Mutoh	[2]
12	Kazuteru Namba	[21] [22] [32]
13	Mariko Numakami	[27]
14	Hiroyuki Ohde	[31]
15	Dhiraj K. Pradhan	[6]
16	T. R. N. Rao (Thammavarapu R. N. Rao)	[5]
17	Tepparit Ritthongpitak	[15] [17]
18	Kiattichai Saowapa	[18]
19	Kazuyoshi Suzuki	[30] [33] [40]
20	Masaharu Tanaka	[10] [12]
21	Ganesan Umanesan	[19] [23] [24] [28]
22	Yu-Lun Wan	[29]

Colors in the list of coauthors

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