 | 2011 |
| 6 |  | Chen Kong Teh,
Tetsuya Fujita,
Hiroyuki Hara,
Mototsugu Hamada:
A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS.
ISSCC 2011: 338-340 |
| 5 |  | Yu Kikuchi,
Makoto Takahashi,
Tomohisa Maeda,
Masatoshi Fukuda,
Yasuhiro Koshio,
Hiroyuki Hara,
Hideho Arakida,
Hideaki Yamamoto,
Yousuke Hagiwara,
Tetsuya Fujita,
Manabu Watanabe,
Hirokazu Ezawa,
Takayoshi Shimazawa,
Yasuo Ohara,
Takashi Miyamori,
Mototsugu Hamada,
Masafumi Takahashi,
Yukihito Oowaki:
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM.
J. Solid-State Circuits 46(1): 32-41 (2011) |
| 2010 |
| 4 |  | Yu Kikuchi,
Makoto Takahashi,
Tomohisa Maeda,
Hiroyuki Hara,
Hideho Arakida,
Hideaki Yamamoto,
Yousuke Hagiwara,
Tetsuya Fujita,
Manabu Watanabe,
Takayoshi Shimazawa,
Yasuo Ohara,
Takashi Miyamori,
Mototsugu Hamada,
Yukihito Oowaki:
A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm.
ISSCC 2010: 326-327 |
| 2006 |
| 3 |  | C. K. Teh,
Mototsugu Hamada,
Tetsuya Fujita,
Hiroyuki Hara,
N. Ikumi,
Yukihito Oowaki:
Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems.
IEEE Trans. VLSI Syst. 14(12): 1379-1383 (2006) |
| 1996 |
| 2 |  | Tadahiro Kuroda,
Tetsuya Fujita,
Shinji Mita,
Toshiaki Mori,
Kenji Matsuo,
Masakazu Kakumu,
Takayasu Sakurai:
Substrate noise influence on circuit performance in variable threshold-voltage scheme.
ISLPED 1996: 309-312 |
| 1988 |
| 1 |  | Robert H. Halstead Jr.,
Tetsuya Fujita:
MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing.
ISCA 1988: 443-451 |