Shinobu Fujita

	2011
13		Igor Loi, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, Luca Benini: Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip. IEEE Trans. on CAD of Integrated Circuits and Systems 30(1): 124-134 (2011)
	2010
12		Shinobu Fujita, Shinichi Yasuda, Dae Sung Lee, Xiangyu Chen, Deji Akinwande, H.-S. Philip Wong: Detachable nano-carbon chip with ultra low power. DAC 2010: 631-632
11		Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita: High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). FPGA 2010: 291
10		Kumiko Nomura, Keiko Abe, Shinobu Fujita, Yasuhiko Kurosawa, Atsushi Kageshima: Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies. ISCAS 2010: 2876-2879
	2009
9		Shinobu Fujita: Nano-electronics challenge chip designers meet real nano-electronics in 2010s? DATE 2009: 431-432
8		Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger: CMOS vs Nano: comrades or rivals? FPGA 2009: 121-122
7		Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto: Perspectives and Issues in 3D-IC from Designers' Point of View. ISCAS 2009: 73-76
	2008
6		Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini: A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. ICCAD 2008: 598-602
5		Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima: ROM based logic (RBL) design: High-performance and low-power adders. ISCAS 2008: 796-799
	2007
4		Toshio Mochizuki, Hiroshi Kato, Kazaru Yaegashi, Toshihisa Nishimori, Yusuke Nagamori, Shinobu Fujita: ProBoPortable: does the cellular phone software promote emergent division of labor in project-based learning? CSCL 2007: 516-518
3		Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee: Prospect of ballistic CNFET in high performance applications: Modeling and analysis. JETC 3(3): (2007)
	2006
2		Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee: Modeling and analysis of circuit performance of ballistic CNFET. DAC 2006: 717-722
1		Ryuji Ohba, Daisuke Matsushita, Koichi Muraoka, Shinichi Yasuda, Tetsufumi Tanamoto, Ken Uchida, Shinobu Fujita: Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation. ISVLSI 2006: 231-236

Coauthor Index

1	Keiko Abe	[7] [10] [11]
2	Deji Akinwande	[12]
3	Federico Angiolini	[13]
4	Kaustav Banerjee	[8]
5	Luca Benini	[6] [13]
6	Deming Chen	[8]
7	Xiangyu Chen	[12]
8	Mojy C. Chian	[8]
9	André DeHon	[8]
10	James Hutchby	[8]
11	Kazutaka Ikegami	[11]
12	Atsushi Kageshima	[10]
13	Hiroshi Kato	[4]
14	Atsuhiro Kinoshita	[11]
15	Yasuhiko Kurosawa	[10]
16	Dae Sung Lee	[12]
17	Thomas Lee	[2] [3]
18	Thomas H. Lee	[6]
19	Igor Loi	[6] [13]
20	Daisuke Matsushita	[1]
21	Subhasish Mitra	[6] [13]
22	Toshio Mochizuki	[4]
23	Koichi Muraoka	[1]
24	Yusuke Nagamori	[4]
25	Toshihisa Nishimori	[4]
26	Hirotaka Nishino	[11]
27	Kumiko Nomura	[7] [10]
28	Ryuji Ohba	[1]
29	Masaki Okajima	[2] [3] [5]
30	Bipul Chandra Paul (Bipul C. Paul)	[2] [3] [5]
31	Tetsufumi Tanamoto	[1] [7] [11]
32	Russell Tessier	[8]
33	Steve Trimberger	[8]
34	Ken Uchida	[1]
35	H.-S. Philip Wong	[12]
36	Kazaru Yaegashi	[4]
37	Shinichi Yasuda	[1] [7] [11] [12]

Colors in the list of coauthors

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