Hiromu Fujioka

	2007
12		Koji Nakamae, Masaki Chikahisa, Hiromu Fujioka: Estimation of electron probe profile from SEM image through wavelet multiresolution analysis for inline SEM inspection. Image Vision Comput. 25(7): 1117-1123 (2007)
	2003
11		Youhei Zenda, Koji Nakamae, Hiromu Fujioka: Cost Optimum Embedded DRAM Design by Yield Analysis. MTDT 2003: 20-
10		Katsuyoshi Miura, Tomoyuki Kobatake, Koji Nakamae, Hiromu Fujioka: A low energy FIB processing, repair, and test system. Microelectronics Reliability 43(9-11): 1627-1631 (2003)
	2002
9		Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka: CAD navigation system, for backside waveform probing of CMOS devices. Microelectronics Reliability 42(9-11): 1679-1684 (2002)
	2001
8		Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka: Development of an EB/FIB Integrated Test System. Microelectronics Reliability 41(9-10): 1489-1494 (2001)
	2000
7		Koji Nakamae, Takashi Ishimura, Hiromu Fujioka: EB tester fault localization algorithm for combinational circuits by utilizing fault simulation and test pattern sequence for EB tester. Systems and Computers in Japan 31(8): 41-48 (2000)
	1999
6		Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka: Intelligent EB Test System for Automatic VLSI Fault Tracing. Asian Test Symposium 1999: 335-341
	1998
5		Koji Nakamae, Shinji Yokoyama, Atsushi Onishi, Hiromu Fujioka: Knowledge-based circuit recognition from standard-cell design CMOS VLSI optical microscope images. Systems and Computers in Japan 29(4): 70-78 (1998)
	1997
4		Katsuyoshi Miura, Kohei Nakata, Koji Nakamae, Hiromu Fujioka: Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data. Asian Test Symposium 1997: 162-167
3		Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka: Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System. J. Electronic Testing 10(3): 255-269 (1997)
	1996
2		Hiromu Fujioka, Koji Nakamae, Akio Higashi: Effects of Multi-Product, Small-Sized Production of LSIs Packaged in Various Packages on the Final Test Process Efficiency and Cost. ITC 1996: 793-799
1		Koji Nakamae, Homare Sakamoto, Hiromu Fujioka: How ATE Planning Affects LSI Manufacturing Cost. IEEE Design & Test of Computers 13(4): 66-73 (1996)

Coauthor Index

1	Masaki Chikahisa	[12]
2	Akio Higashi	[2]
3	Takashi Ishimura	[7]
4	Tomoyuki Kobatake	[10]
5	Katsuyoshi Miura	[3] [4] [6] [8] [9] [10]
6	Koji Nakamae	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
7	Kohei Nakata	[4]
8	Atsushi Onishi	[5]
9	Homare Sakamoto	[1]
10	Shinji Yokoyama	[5]
11	Youhei Zenda	[11]

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