Takeshi Fujino

	2012
7		Anh-Tuan Hoang, Takeshi Fujino: Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA. FPGA 2012: 1-10
6		Mitsuru Shiozaki, Kota Furuhashi, Takahiko Murayama, Akitaka Fukushima, Masaya Yoshikawa, Takeshi Fujino: High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications. IEICE Transactions 95-C(4): 468-477 (2012)
	2011
5		Katsuhiko Iwai, Mitsuru Shiozaki, Anh-Tuan Hoang, Kenji Kojima, Takeshi Fujino: Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL. HOST 2011: 28-33
4		Kota Furuhashi, Mitsuru Shiozaki, Akitaka Fukushima, Takahiko Murayama, Takeshi Fujino: The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with Delay-Time Measurement. ISCAS 2011: 2325-2328
3		Masaya Yoshikawa, Takeshi Fujino: Placement Tool Dedicated for a Via-Programmable Logic Device VPEX. I. J. Comput. Appl. 18(4): 218-226 (2011)
	2010
2		Masaya Yoshikawa, Yuichi Kokusyo, Takeshi Fujino: Placement Tool Dedicated for a Via-programmable Logic Device VPEX. CAINE 2010: 21-25
	2008
1		Akihiro Nakamura, Masahide Kawarasaki, Kouta Ishibashi, Masaya Yoshikawa, Takeshi Fujino: Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing. IEICE Transactions 91-C(4): 509-516 (2008)

Coauthor Index

1	Akitaka Fukushima	[4] [6]
2	Kota Furuhashi	[4] [6]
3	Anh-Tuan Hoang	[5] [7]
4	Kouta Ishibashi	[1]
5	Katsuhiko Iwai	[5]
6	Masahide Kawarasaki	[1]
7	Kenji Kojima	[5]
8	Yuichi Kokusyo	[2]
9	Takahiko Murayama	[4] [6]
10	Akihiro Nakamura	[1]
11	Mitsuru Shiozaki	[4] [5] [6]
12	Masaya Yoshikawa	[1] [2] [3] [6]

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