Eby G. Friedman

	2012
181		Renatas Jakushokas, Eby G. Friedman: Link breaking methodology: mitigating noise within power networks. ACM Great Lakes Symposium on VLSI 2012: 129-134
180		Selçuk Köse, Eby G. Friedman, Simon Tarn, Sally Pinzon, Bruce McDermott: An area efficient on-chip hybrid voltage regulator. ISQED 2012: 398-403
179		Selçuk Köse, Eby G. Friedman: Efficient algorithms for fast IR drop analysis exploiting locality. Integration 45(2): 149-161 (2012)
178		Emre Salman, Eby G. Friedman: Utilizing interdependent timing constraints to enhance robustness in synchronous circuits. Microelectronics Journal 43(2): 119-127 (2012)
177		Victoria Vishnyakov, Eby G. Friedman, Avinoam Kolodny: Multi-aggressor capacitive and inductive coupling noise modeling and mitigation. Microelectronics Journal 43(4): 235-243 (2012)
	2011
176		Selçuk Köse, Eby G. Friedman: Fast algorithms for IR voltage drop analysis exploiting locality. DAC 2011: 996-1001
175		Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman: Memristor-based IMPLY logic design procedure. ICCD 2011: 142-147
174		Ioannis Savidis, Vasilis F. Pavlidis, Eby G. Friedman: Clock distribution models of 3-D integrated systems. ISCAS 2011: 2225-2228
173		Selçuk Köse, Eby G. Friedman: Distributed power network co-design with on-chip power supplies and decoupling capacitors. SLIP 2011: 1-5
172		Jonathan Rosenfeld, Eby G. Friedman: Linear and Switch-Mode Conversion in 3-D Circuits. IEEE Trans. VLSI Syst. 19(11): 2095-2108 (2011)
171		Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman: Clock Distribution Networks in 3-D Integrated Systems. IEEE Trans. VLSI Syst. 19(12): 2256-2266 (2011)
170		Renatas Jakushokas, Eby G. Friedman: Multi-Layer Interdigitated Power Distribution Networks. IEEE Trans. VLSI Syst. 19(5): 774-786 (2011)
169		Jonathan Rosenfeld, Eby G. Friedman: A Distributed Filter Within a Switching Converter for Application to 3-D Integrated Circuits. IEEE Trans. VLSI Syst. 19(6): 1075-1085 (2011)
168		Selçuk Köse, Emre Salman, Eby G. Friedman: Shielding Methodologies in the Presence of Power/Ground Noise. IEEE Trans. VLSI Syst. 19(8): 1458-1468 (2011)
167		Selçuk Köse, Eby G. Friedman: Effective Resistance of a Two Layer Mesh. IEEE Trans. on Circuits and Systems 58-II(11): 739-743 (2011)
166		Jinhui Wang, Ioannis Savidis, Eby G. Friedman: Thermal analysis of oxide-confined VCSEL arrays. Microelectronics Journal 42(5): 820-825 (2011)
	2010
165		Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman: Timing-driven variation-aware nonuniform clock mesh synthesis. ACM Great Lakes Symposium on VLSI 2010: 15-20
164		Renatas Jakushokas, Eby G. Friedman: Line width optimization for interdigitated power/ground networks. ACM Great Lakes Symposium on VLSI 2010: 329-334
163		Selçuk Köse, Eby G. Friedman: On-chip point-of-load voltage regulator for distributed power supplies. ACM Great Lakes Symposium on VLSI 2010: 377-380
162		Emre Salman, Eby G. Friedman: Methodology to achieve higher tolerance to delay variations in synchronous circuits. ACM Great Lakes Symposium on VLSI 2010: 447-452
161		Gregory Sizikov, Avinoam Kolodny, Eby G. Friedman, Michael Zelikson: Efficiency optimization of integrated DC-DC buck converters. ICECS 2010: 1208-1211
160		Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu, Michael C. Huang, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore: An intra-chip free-space optical interconnect. ISCA 2010: 94-105
159		Renatas Jakushokas, Eby G. Friedman: Globally integrated power and clock distribution network. ISCAS 2010: 1751-1754
158		Renatas Jakushokas, Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin, Cynthia L. Recker: Compact substrate models for efficient noise coupling and signal isolation analysis. ISCAS 2010: 2346-2349
157		Selçuk Köse, Eby G. Friedman: An area efficient fully monolithic hybrid voltage regulator. ISCAS 2010: 2718-2721
156		Renatas Jakushokas, Eby G. Friedman: Methodology for multi-layer interdigitated power and ground network design. ISCAS 2010: 3208-3211
155		Selçuk Köse, Eby G. Friedman: Fast algorithms for power grid analysis based on effective resistance. ISCAS 2010: 3661-3664
154		Selçuk Köse, Eby G. Friedman: Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors. SoCC 2010: 15-18
153		Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. IEEE Trans. VLSI Syst. 18(5): 689-696 (2010)
152		Renatas Jakushokas, Eby G. Friedman: Resource Based Optimization for Simultaneous Shield and Repeater Insertion. IEEE Trans. VLSI Syst. 18(5): 742-749 (2010)
151		Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. IEEE Trans. VLSI Syst. 18(8): 1262 (2010)
	2009
150		Renatas Jakushokas, Eby G. Friedman: Simultaneous shield and repeater insertion. ACM Great Lakes Symposium on VLSI 2009: 15-20
149		Eby G. Friedman: Design challenges in high performance three-dimensional circuits. ACM Great Lakes Symposium on VLSI 2009: 281-282
148		Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman: Power efficient tree-based crosslinks for skew reduction. ACM Great Lakes Symposium on VLSI 2009: 285-290
147		Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Contact merging algorithm for efficient substrate noise analysis in large scale circuits. ACM Great Lakes Symposium on VLSI 2009: 9-14
146		Renatas Jakushokas, Eby G. Friedman: Minimizing Noise Via Shield and Repeater Insertion. ISCAS 2009: 2265-2268
145		Selçuk Köse, Emre Salman, Eby G. Friedman: Shielding Methodologies in the Presence of Power/Ground Noise. ISCAS 2009: 2277-2280
144		Jonathan Rosenfeld, Eby G. Friedman: On-chip DC-DC converters for three-dimensional ICs. ISQED 2009: 759-764
143		Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits. IEEE Trans. VLSI Syst. 17(10): 1405-1418 (2009)
142		Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling. IEEE Trans. VLSI Syst. 17(10): 1559-1564 (2009)
141		Jonathan Rosenfeld, Eby G. Friedman: Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology. IEEE Trans. VLSI Syst. 17(2): 181-193 (2009)
140		Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance. IEEE Trans. on Circuits and Systems 56-I(5): 997-1004 (2009)
139		Renatas Jakushokas, Eby G. Friedman: Inductance Model of Interdigitated Power and Ground Distribution Networks. IEEE Trans. on Circuits and Systems 56-II(7): 585-589 (2009)
138		Guoqing Chen, Eby G. Friedman: Transient Response of a Distributed RLC Interconnect Based on Direct Pole Extraction. Journal of Circuits, Systems, and Computers 18(7): 1263-1285 (2009)
	2008
137		Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Equivalent rise time for resonance in power/ground noise estimation. ISCAS 2008: 2422-2425
136		Guoqing Chen, Eby G. Friedman: Transient simulation of on-chip transmission lines via exact pole extraction. ISCAS 2008: 2757-2760
135		Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Input port reduction for efficient substrate extraction in large scale IC's. ISCAS 2008: 376-379
134		Ioannis Savidis, Eby G. Friedman: Electrical modeling and characterization of 3-D vias. ISCAS 2008: 784-787
133		Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates. ISQED 2008: 261-266
132		Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Timing optimization in logic with interconnect. SLIP 2008: 19-26
131		Alexander Lavzin, Mücahit Kozak, Eby G. Friedman: A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators. SoCC 2008: 267-270
130		Selçuk Köse, Emre Salman, Zeljko Ignjatovic, Eby G. Friedman: Pseudo-random clocking to enhance signal integrity. SoCC 2008: 47-50
129		Mikhail Popovich, Eby G. Friedman: Nanoscale on-chip decoupling capacitors. SoCC 2008: 51-54
128		Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs. IEEE Trans. VLSI Syst. 16(12): 1717-1721 (2008)
127		Mikhail Popovich, Michael Sotman, Avinoam Kolodny, Eby G. Friedman: Effective Radii of On-Chip Decoupling Capacitors. IEEE Trans. VLSI Syst. 16(7): 894-907 (2008)
126		Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny: On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits. IEEE Trans. VLSI Syst. 16(7): 908-921 (2008)
125		Guoqing Chen, Eby G. Friedman: Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis. IEEE Trans. on Circuits and Systems 55-II(1): 26-30 (2008)
124		Vasilis F. Pavlidis, Eby G. Friedman: Timing-driven via placement heuristics for three-dimensional ICs. Integration 41(4): 489-508 (2008)
	2007
123		Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs. ICCAD 2007: 811-816
122		Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Substrate Noise Reduction Based On Noise Aware Cell Design. ISCAS 2007: 3227-3230
121		Jonathan Rosenfeld, Eby G. Friedman: Quasi-Resonant Interconnects: A Low Power Design Methodology. ISCAS 2007: 641-644
120		Vasilis F. Pavlidis, Eby G. Friedman: 3-D Topologies for Networks-on-Chip. IEEE Trans. VLSI Syst. 15(10): 1081-1090 (2007)
119		Jonathan Rosenfeld, Eby G. Friedman: Design Methodology for Global Resonant H-Tree Clock Distribution Networks. IEEE Trans. VLSI Syst. 15(2): 135-148 (2007)
118		Emre Salman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar, Eby G. Friedman: Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1114-1125 (2007)
117		Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman: Predictions of CMOS compatible on-chip optical interconnect. Integration 40(4): 434-446 (2007)
116		Magdy A. El-Moursy, Eby G. Friedman: Wire shaping of RLC interconnects. Integration 40(4): 461-472 (2007)
	2006
115		Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu: Maximum effective distance of on-chip decoupling capacitors in power distribution grids. ACM Great Lakes Symposium on VLSI 2006: 173-179
114		Jonathan Rosenfeld, Eby G. Friedman: Sensitivity evaluation of global resonant H-tree clock distribution networks. ACM Great Lakes Symposium on VLSI 2006: 192-197
113		Jonathan Rosenfeld, Eby G. Friedman: Design methodology for global resonant H-tree clock distribution networks. ISCAS 2006
112		Guoqing Chen, Eby G. Friedman: Effective capacitance of RLC loads for estimating short-circuit power. ISCAS 2006
111		Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman: On-die decoupling capacitance: frequency domain analysis of activity radius. ISCAS 2006
110		Magdy A. El-Moursy, Eby G. Friedman: Optimum wire tapering for minimum power dissipation in RLC interconnects. ISCAS 2006
109		Vasilis F. Pavlidis, Eby G. Friedman: Via placement for minimum interconnect delay in three-dimensional (3D) circuits. ISCAS 2006
108		Emre Salman, Eby G. Friedman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar: Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times. ISQED 2006: 159-164
107		Guoqing Chen, Eby G. Friedman: Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints. IEEE Trans. VLSI Syst. 14(2): 161-172 (2006)
106		Mikhail Popovich, Eby G. Friedman: Decoupling capacitors for multi-voltage power distribution systems. IEEE Trans. VLSI Syst. 14(3): 217-228 (2006)
105		Junmou Zhang, Eby G. Friedman: Crosstalk modeling for coupled RLC interconnects with application to shield insertion. IEEE Trans. VLSI Syst. 14(6): 641-646 (2006)
104		Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman: Sizing CMOS inverters with Miller Effect and Threshold voltage Variations. Journal of Circuits, Systems, and Computers 15(3): 437-454 (2006)
	2005
103		Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny: On-chip power distribution grids with multiple supply voltages for high performance integrated circuits. ACM Great Lakes Symposium on VLSI 2005: 2-7
102		Vasilis F. Pavlidis, Eby G. Friedman: Interconnect delay minimization through interlayer via placement in 3-D ICs. ACM Great Lakes Symposium on VLSI 2005: 20-25
101		Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva Narendra: Cascode buffer for monolithic voltage conversion operating at high input supply voltages. ISCAS (1) 2005: 464-467
100		Guoqing Chen, Eby G. Friedman: Low power repeaters driving RLC interconnects with delay and bandwidth constraints. ISCAS (1) 2005: 596-599
99		Radu M. Secareanu, S. K. Banerjee, Olin L. Hartin, Francisco V. Fernández, Eby G. Friedman: Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment. ISCAS (1) 2005: 612-615
98		Mikhail Popovich, Eby G. Friedman: Noise coupling in multi-voltage power distribution systems with decoupling capacitors. ISCAS (1) 2005: 620-623
97		Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi: Electrical and optical on-chip interconnects in scaled microprocessors. ISCAS (3) 2005: 2514-2517
96		Guoqing Chen, Eby G. Friedman: A Fourier series-based RLC interconnect model for periodic signals. ISCAS (4) 2005: 4126-4129
95		Mikhail Popovich, Eby G. Friedman: Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems. ISQED 2005: 334-339
94		Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi: Predictions of CMOS compatible on-chip optical interconnect. SLIP 2005: 13-20
93		Magdy A. El-Moursy, Eby G. Friedman: Shielding effect of on-chip interconnect inductance. IEEE Trans. VLSI Syst. 13(3): 396-400 (2005)
92		Magdy A. El-Moursy, Eby G. Friedman: Exponentially tapered H-tree clock distribution networks. IEEE Trans. VLSI Syst. 13(8): 971-975 (2005)
91		Guoqing Chen, Eby G. Friedman: An RLC interconnect model based on fourier analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 170-183 (2005)
90		Volkan Kursun, Vivek De, Eby G. Friedman, Siva G. Narendra: Monolithic voltage conversion in low-voltage CMOS technologies. Microelectronics Journal 36(9): 863-867 (2005)
	2004
89		Junmou Zhang, Simon R. Cooper, Andrew R. LaPietra, Michael W. Mattern, Robert M. Guidash, Eby G. Friedman: A low power thyristor-based CMOS programmable delay element. ISCAS (1) 2004: 769-772
88		Volkan Kursun, Eby G. Friedman: Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage. ISCAS (2) 2004: 417-420
87		Junmou Zhang, Eby G. Friedman: Decoupling technique and crosstalk analysis for coupled RLC interconnects. ISCAS (2) 2004: 521-524
86		Junmou Zhang, Eby G. Friedman: Effect of shield insertion on reducing crosstalk noise between coupled interconnects. ISCAS (2) 2004: 529-532
85		Magdy A. El-Moursy, Eby G. Friedman: Exponentially tapered H-tree clock distribution networks. ISCAS (2) 2004: 601-604
84		Volkan Kursun, Eby G. Friedman: Forward body biased keeper for enhanced noise immunity in domino logic circuits. ISCAS (2) 2004: 917-920
83		Mücahit Kozak, Eby G. Friedman: Design and simulation of Fractional-N PLL frequency synthesizers. ISCAS (4) 2004: 780-783
82		Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman: Low power flexible Rake receivers for WCDMA. ISCAS (4) 2004: 97-100
81		Volkan Kursun, Eby G. Friedman: Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits. ISQED 2004: 104-109
80		Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman: High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. ISQED 2004: 517-521
79		Dimitrios Velenis, Eby G. Friedman: Buffer Sizing for Crosstalk Induced Delay Uncertainty. PATMOS 2004: 750-759
78		Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman: Substrate coupling in digital circuits in mixed-signal smart-power systems. IEEE Trans. VLSI Syst. 12(1): 67-78 (2004)
77		Andrey V. Mezhiba, Eby G. Friedman: Impedance characteristics of power distribution grids in nanoscale integrated circuits. IEEE Trans. VLSI Syst. 12(11): 1148-1155 (2004)
76		Magdy A. El-Moursy, Eby G. Friedman: Power characteristics of inductive interconnect. IEEE Trans. VLSI Syst. 12(12): 1295-1306 (2004)
75		Andrey V. Mezhiba, Eby G. Friedman: Scaling trends of on-chip power distribution noise. IEEE Trans. VLSI Syst. 12(4): 386-394 (2004)
74		Volkan Kursun, Eby G. Friedman: Sleep switch dual threshold Voltage domino logic with reduced standby leakage current. IEEE Trans. VLSI Syst. 12(5): 485-496 (2004)
73		Magdy A. El-Moursy, Eby G. Friedman: Optimum wire sizing of RLC interconnect with repeaters . Integration 38(2): 205-225 (2004)
72		Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman: Complex +/-1 Multiplier Based on Signed-Binary Transformations. VLSI Signal Processing 38(1): 13-24 (2004)
	2003
71		Magdy A. El-Moursy, Eby G. Friedman: Shielding effect of on-chip interconnect inductance. ACM Great Lakes Symposium on VLSI 2003: 165-170
70		Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman: Orthogonal code generator for 3G wireless transceivers. ACM Great Lakes Symposium on VLSI 2003: 229-232
69		Magdy A. El-Moursy, Eby G. Friedman: Optimum wire sizing of RLC interconnect with repeaters. ACM Great Lakes Symposium on VLSI 2003: 27-32
68		Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman: Reduced Delay Uncertainty in High Performance Clock Distribution Networks. DATE 2003: 10068-10075
67		Magdy A. El-Moursy, Eby G. Friedman: Inductive interconnect width optimization for low power. ISCAS (5) 2003: 273-276
66		Andrey V. Mezhiba, Eby G. Friedman: Electrical characteristics of multi-layer power distribution grids. ISCAS (5) 2003: 473-476
65		Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman: Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. ISQED 2003: 279-
64		Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman: Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic. IWSOC 2003: 70-75
63		David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster: Dynamically Tuning Processor Resources with Adaptive Processing. IEEE Computer 36(12): 49-58 (2003)
62		Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman: Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. IEEE Trans. VLSI Syst. 11(3): 514-522 (2003)
61		Volkan Kursun, Eby G. Friedman: Domino logic with variable threshold voltage keeper. IEEE Trans. VLSI Syst. 11(6): 1080-1093 (2003)
60		Yehea I. Ismail, Eby G. Friedman: On the Extraction of On-Chip Inductance. Journal of Circuits, Systems, and Computers 12(1): 31-40 (2003)
	2002
59		Andrey V. Mezhiba, Eby G. Friedman: Properties of on-chip inductive current loops. ACM Great Lakes Symposium on VLSI 2002: 12-17
58		Volkan Kursun, Eby G. Friedman: Low swing dual threshold voltage domino logic. ACM Great Lakes Symposium on VLSI 2002: 47-52
57		Boris D. Andreev, Eby G. Friedman, Edward L. Titlebaum: Efficient implementation of a complex ±1 multiplier. ACM Great Lakes Symposium on VLSI 2002: 83-88
56		Andrey V. Mezhiba, Eby G. Friedman: Inductance/area/resistance tradeoffs in high performance power distribution grids. ISCAS (1) 2002: 101-104
55		Weize Xu, Eby G. Friedman: A substrate noise circuit for accurately testing mixed-signal ICs. ISCAS (1) 2002: 145-148
54		Roy Mader, Eby G. Friedman, Ami Litman, Ivan S. Kourtev: Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits. ISCAS (1) 2002: 357-360
53		Andrey V. Mezhiba, Eby G. Friedman: Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits. ISQED 2002: 316-321
52		Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman: Managing static leakage energy in microprocessor functional units. MICRO 2002: 321-332
51		Andrey V. Mezhiba, Eby G. Friedman: Scaling trends of on-chip Power distribution noise. SLIP 2002: 47-53
50		Kevin T. Tang, Eby G. Friedman: Simultaneous switching noise in on-chip CMOS power distribution networks. IEEE Trans. VLSI Syst. 10(4): 487-493 (2002)
49		Andrey V. Mezhiba, Eby G. Friedman: Inductive properties of high-performance power distribution grids. IEEE Trans. VLSI Syst. 10(6): 762-776 (2002)
48		Yehea I. Ismail, Eby G. Friedman: DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 131-144 (2002)
47		Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Retiming and clock scheduling for digital circuit optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 184-203 (2002)
46		Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, V. Adler, F. Baez, Eby G. Friedman: Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. Journal of Circuits, Systems, and Computers 11(3): 231-246 (2002)
45		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Inductance Effects in RLC Trees. Journal of Circuits, Systems, and Computers 11(3): 305- (2002)
	2001
44		Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou: A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. ISCAS (4) 2001: 422-425
43		Kevin T. Tang, Eby G. Friedman: Estimation of transient voltage fluctuations in the CMOS-based power distribution networks. ISCAS (5) 2001: 463-466
42		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Exploiting the on-chip inductance in high-speed clock distribution networks. IEEE Trans. VLSI Syst. 9(6): 963-973 (2001)
	2000
41		Kevin T. Tang, Eby G. Friedman: Noise estimation due to signal activity for capacitively coupled CMOS logic gates. ACM Great Lakes Symposium on VLSI 2000: 171-176
40		Radu M. Secareanu, Eby G. Friedman: Transparent repeaters. ACM Great Lakes Symposium on VLSI 2000: 63-66
39		Yehea I. Ismail, Eby G. Friedman: Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. IEEE Trans. VLSI Syst. 8(2): 195-206 (2000)
38		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Equivalent Elmore delay for RLC trees. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 83-97 (2000)
37		Kevin T. Tang, Eby G. Friedman: Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections. Integration 29(2): 131-165 (2000)
	1999
36		Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Maximizing Performance by Retiming and Clock Skew Scheduling. DAC 1999: 231-236
35		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Equivalent Elmore Delay for RLC Trees. DAC 1999: 715-720
34		Yehea I. Ismail, Eby G. Friedman: Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits. DAC 1999: 721-724
33		Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. DATE 1999: 643-649
32		Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman: Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems. Great Lakes Symposium on VLSI 1999: 314-317
31		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Inductance Effects in RLC Trees. Great Lakes Symposium on VLSI 1999: 56-59
30		Ivan S. Kourtev, Eby G. Friedman: Clock skew scheduling for improved reliability via quadratic programming. ICCAD 1999: 239-243
29		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Repeater insertion in tree structured inductive interconnect. ICCAD 1999: 420-424
28		Radu M. Secareanu, Eby G. Friedman, Juan Becerra, Scott Warner: A universal CMOS voltage interface circuit. ISCAS (1) 1999: 242-245
27		Kevin T. Tang, Eby G. Friedman: Peak noise prediction in loosely coupled interconnect [VLSI circuits]. ISCAS (1) 1999: 541-544
26		Radu M. Secareanu, Eby G. Friedman: A high precision CMOS current mirror/divider. ISCAS (2) 1999: 314-317
25		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Signal waveform characterization in RLC trees. ISCAS (6) 1999: 190-193
24		Yehea I. Ismail, Eby G. Friedman: Repeater insertion in RLC lines for minimum propagation delay. ISCAS (6) 1999: 404-407
23		Kevin T. Tang, Eby G. Friedman: Interconnect coupling noise in CMOS VLSI circuits. ISPD 1999: 48-53
22		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Figures of merit to characterize the importance of on-chip inductance. IEEE Trans. VLSI Syst. 7(4): 442-449 (1999)
	1998
21		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Figures of Merit to Characterize the Importance of On-Chip Inductance. DAC 1998: 560-565
20		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. Great Lakes Symposium on VLSI 1998: 39-44
19		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Power dissipated by CMOS gates driving lossless transmission lines. ISLPED 1998: 139-142
	1997
18		Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.: Incorporating interconnect, register, and clock distribution delays into the retiming process. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 105-120 (1997)
17		Eby G. Friedman: High Performance Clock Distribution Networks. VLSI Signal Processing 16(2-3): 113-116 (1997)
16		José Luis Neves, Eby G. Friedman: Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations. VLSI Signal Processing 16(2-3): 149-161 (1997)
15		Kris Gaj, Eby G. Friedman, Marc J. Feldman: Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits. VLSI Signal Processing 16(2-3): 247-276 (1997)
	1996
14		José Luis Neves, Eby G. Friedman: Optimal Clock Skew Scheduling Tolerant to Process Variations. DAC 1996: 623-628
13		José Luis Neves, Eby G. Friedman: Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew. IEEE Trans. VLSI Syst. 4(2): 286-291 (1996)
	1995
12		José Luis Neves, Eby G. Friedman: Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks. ISCAS 1995: 1576-1579
11		Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.: Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay. ISCAS 1995: 1748-1751
10		Brian S. Cherkauer, Eby G. Friedman: A unified design methodology for CMOS tapered buffers. IEEE Trans. VLSI Syst. 3(1): 99-111 (1995)
	1994
9		Tolga Soyata, Eby G. Friedman: Retiming with non-zero clock skew, variable register, and interconnect delay. ICCAD 1994: 234-241
8		Eby G. Friedman, Sung-Mo Kang, Eric A. Vittoz, David J. Allstot, Erik P. Harris, Ran-Hong Yan: Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS. ISCAS 1994: 1-6
7		Brian S. Cherkauer, Eby G. Friedman: Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design. ISCAS 1994: 111-114
6		José Luis Neves, Eby G. Friedman: Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew. ISCAS 1994: 175-178
5		Brian S. Cherkauer, Eby G. Friedman: Channel width tapering of serially connected MOSFET's with emphasis on power dissipation. IEEE Trans. VLSI Syst. 2(1): 100-114 (1994)
	1993
4		Eby G. Friedman: Clock Distribution Design in VLSI Circuits. An Overview. ISCAS 1993: 1475-1478
3		Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.: Integration of Clock Skew and Register Delays into a Retiming Algorithm. ISCAS 1993: 1483-1486
2		Brian S. Cherkauer, Eby G. Friedman: The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs. ISCAS 1993: 2110-2113
	1991
1		Eby G. Friedman, James H. Mulligan Jr.: Clock frequency and latency in synchronous digital systems. IEEE Transactions on Signal Processing 39(4): 930-934 (1991)

Coauthor Index

1	Ameer Abdelhadi	[165]
2	V. Adler	[46]
3	David H. Albonesi	[52] [63] [94] [97] [117]
4	David J. Allstot	[8]
5	Boris D. Andreev	[57] [64] [70] [72] [82] [104]
6	F. Baez	[46]
7	Rajeev Balasubramonian	[63]
8	S. K. Banerjee	[99]
9	Juan Becerra	[28] [32] [78]
10	Rebecca Berman	[160]
11	Pradip Bose	[63]
12	Cathie Burke	[78]
13	Alper Buyuktosunoglu	[63]
14	Guoqing Chen	[91] [94] [96] [97] [100] [107] [112] [117] [125] [136] [138]
15	Hui Chen	[94] [97] [117]
16	Brian S. Cherkauer	[2] [5] [7] [10]
17	Berkehan Ciftcioglu	[160]
18	Peter W. Cook	[63]
19	Simon R. Cooper	[89]
20	Ali Dasdan	[108] [118]
21	Vivek De (Vivek K. De)	[62] [65] [80] [90] [101]
22	Steven G. Dropsho (Steve Dropsho)	[52] [63]
23	Sandhya Dwarkadas	[52] [63]
24	Magdy A. El-Moursy	[67] [69] [71] [73] [76] [85] [92] [93] [110] [116]
25	Philippe M. Fauchet	[94] [97] [117]
26	Marc J. Feldman	[15]
27	Francisco V. Fernández (Francisco Vidal Fernández Fernández)	[99]
28	Kris Gaj	[15]
29	Alok Garg	[160]
30	Ran Ginosar	[132] [148] [151] [153] [165]
31	Robert M. Guidash	[89]
32	Erik P. Harris	[8]
33	Olin L. Hartin	[99] [122] [123] [128] [133] [135] [137] [140] [142] [143] [147] [158]
34	Mikhail Haurylau	[94] [97] [117]
35	Jianyun Hu	[160]
36	Michael C. Huang	[63] [160]
37	Zeljko Ignjatovic	[130]
38	Yehea I. Ismail	[19] [20] [21] [22] [24] [25] [29] [31] [34] [35] [38] [39] [42] [45] [48] [60]
39	Manish Jain	[160]
40	Renatas Jakushokas	[135] [139] [143] [146] [147] [150] [152] [156] [158] [159] [164] [170] [181]
41	Sung-Mo Kang	[8]
42	Avinoam Kolodny	[103] [111] [115] [126] [127] [132] [148] [151] [153] [161] [165] [175] [177]
43	Selçuk Köse	[130] [145] [154] [155] [157] [163] [167] [168] [173] [176] [179] [180]
44	Ivan S. Kourtev	[30] [32] [46] [54] [78]
45	Mücahit Kozak	[83] [131]
46	Kayhan Küçükçakar	[108] [118]
47	Volkan Kursun	[52] [58] [61] [62] [63] [65] [74] [80] [81] [84] [88] [90] [101]
48	Shahar Kvatinsky	[175]
49	Andrew R. LaPietra	[89]
50	Alexander Lavzin	[131]
51	Ami Litman	[54]
52	Peng Liu	[160]
53	Xun Liu	[33] [36] [47]
54	Roy Mader	[54]
55	Grigorios Magklis	[63]
56	Michael W. Mattern	[89]
57	Bruce McDermott	[180]
58	Andrey V. Mezhiba	[49] [51] [53] [56] [59] [66] [75] [77]
59	Duncan Moore	[160]
60	Arkadiy Morgenshtein	[132] [151] [153]
61	Christopher Morton	[32] [78]
62	James H. Mulligan Jr.	[1] [3] [11] [18]
63	Siva Narendra	[65] [80] [101]
64	Siva G. Narendra	[62] [90]
65	Nicholas Nelson	[94] [97] [117]
66	José Luis Neves	[6] [12] [13] [14] [16] [19] [20] [21] [22] [25] [29] [31] [35] [38] [42] [45]
67	Marios C. Papaefthymiou	[33] [36] [44] [47] [68]
68	Vasilis F. Pavlidis	[102] [109] [120] [124] [171] [174]
69	Sally Pinzon	[180]
70	Mikhail Popovich	[95] [98] [103] [106] [111] [115] [123] [126] [127] [128] [129]
71	Cynthia L. Recker	[158]
72	Jonathan Rosenfeld	[113] [114] [119] [121] [141] [144] [169] [172]
73	Emre Salman	[108] [118] [122] [130] [133] [135] [137] [140] [142] [143] [145] [147] [158] [162] [168] [178]
74	Ioannis Savidis	[134] [160] [166] [171] [174]
75	Gerhard Schrom	[101]
76	Stanley Schuster	[63]
77	Michael L. Scott	[63]
78	Scott Seabridge	[78]
79	Radu M. Secareanu	[26] [28] [32] [40] [78] [99] [115] [122] [123] [128] [133] [135] [137] [140] [142] [143] [147] [158]
80	Greg Semeraro	[63]
81	Gregory Sizikov	[161]
82	Michael Sotman	[103] [111] [115] [126] [127]
83	Tolga Soyata	[3] [9] [11] [18]
84	William Staub	[32] [78]
85	Kevin T. Tang	[23] [27] [37] [41] [43] [46] [50]
86	Feroze Taraporevala	[108] [118]
87	Simon Tarn	[180]
88	Thomas Tellier	[32] [78]
89	Edward L. Titlebaum	[57] [64] [70] [72] [82] [104]
90	Inna Vaisband	[148]
91	Dimitrios Velenis	[44] [46] [68] [79]
92	Victoria Vishnyakov	[177]
93	Eric A. Vittoz	[8]
94	Jinhui Wang	[166]
95	Shang Wang	[160]
96	Scott Warner	[28] [78]
97	Thomas E. Watrobski	[32] [78]
98	Uri C. Weiser	[175]
99	Gary Wicks	[160]
100	Hui Wu	[160]
101	Weize Xu	[55]
102	Jing Xue	[160]
103	Ran-Hong Yan	[8]
104	Michael Zelikson	[161]
105	Junmou Zhang	[86] [87] [89] [105]

Colors in the list of coauthors

Last update Wed May 30 22:34:44 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page