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Matthew French Coauthor index pubzone.org

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DBLP keys2012
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLWilliam V. Kritikos, Andrew G. Schmidt, Ron Sass, Erik K. Anderson, Matthew French: Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip. Int. J. Reconfig. Comp. 2012: (2012)
2011
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMark Bucciero, John Paul Walters, Roger Moussalli, Shanyuan Gao, Matthew French: The PowerPC 405 Memory Sentinel and Injection System. FCCM 2011: 154-161
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAndrew G. Schmidt, Bin Huang, Ron Sass, Matthew French: Checkpoint/Restart and Beyond: Resilient High Performance Computing with FPGAs. FCCM 2011: 162-169
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNeil Steiner, Aaron Wood, Hamid Shojaei, Jacob Couch, Peter Athanas, Matthew French: Torc: towards an open-source tool flow. FPGA 2011: 41-44
2010
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAndrew G. Schmidt, William V. Kritikos, Ron Sass, Erik K. Anderson, Matthew French: Merging Programming Models and On-chip Networks to Meet the Programmable and Performance Needs of Multi-core Systems on a Programmable Chip. ReConFig 2010: 334-339
2008
5no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLErik K. Anderson, Matthew French, Dong-In Kang: System on a Programmable Chip Adaptation Through Active Partial Reconfiguration. ERSA 2008: 104-110
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMatthew French, Erik K. Anderson, Dong-In Kang: Autonomous System on a Chip Adaptation through Partial Runtime Reconfiguration. FCCM 2008: 77-86
2006
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMatthew French, Li Wang, Michael J. Wirthlin: Power Visualization, Analysis, and Optimization Tools for FPGAs. FCCM 2006: 185-194
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLLi Wang, Matthew French, Azadeh Davoodi, Deepak Agarwal: FPGA Dynamic Power Minimization through Placement and Routing Constraints. EURASIP J. Emb. Sys. 2006: (2006)
2005
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMatthew French, Li Wang, Tyler Anderson, Michael J. Wirthlin: Post Synthesis Level Power Modeling of FPGAs. FCCM 2005: 281-282

Coauthor Index

1Deepak Agarwal [2]
2Erik K. Anderson [4] [5] [6] [10]
3Tyler Anderson [1]
4Peter M. Athanas (Peter Athanas) [7]
5Mark Bucciero [9]
6Jacob Couch [7]
7Azadeh Davoodi [2]
8Shanyuan Gao [9]
9Bin Huang [8]
10Dong-In Kang [4] [5]
11William V. Kritikos [6] [10]
12Roger Moussalli [9]
13Ron Sass (Ron R. Sass) [6] [8] [10]
14Andrew G. Schmidt [6] [8] [10]
15Hamid Shojaei [7]
16Neil Steiner [7]
17John Paul Walters [9]
18Li Wang [1] [2] [3]
19Michael J. Wirthlin [1] [3]
20Aaron Wood [7]

Colors in the list of coauthors

Last update Wed May 30 22:34:44 2012 CET by the DBLP TeamThis material is Open Data Data released under the ODC-BY 1.0 license — See also our legal information page