 | 2012 |
| 34 |  | Levent Aksoy,
Eduardo Costa,
Paulo F. Flores,
José C. Monteiro:
Design of low-complexity digital finite impulse response filters on FPGAs.
DATE 2012: 1197-1202 |
| 33 |  | Levent Aksoy,
Eduardo Costa,
Paulo F. Flores,
José C. Monteiro:
Optimization Algorithms for the Multiplierless Realization of Linear Transforms.
ACM Trans. Design Autom. Electr. Syst. 17(1): 3 (2012) |
| 32 |  | Levent Aksoy,
Cristiano Lazzari,
Eduardo Costa,
Paulo F. Flores,
José Monteiro:
High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications.
Integration 45(3): 294-306 (2012) |
| 31 |  | Nuno Sebastião,
Nuno Roma,
Paulo F. Flores:
Hardware accelerator architecture for simultaneous short-read DNA sequences alignment with enhanced traceback phase.
Microprocessors and Microsystems - Embedded Hardware Design 36(2): 96-109 (2012) |
| 2011 |
| 30 |  | Levent Aksoy,
Cristiano Lazzari,
Eduardo Costa,
Paulo F. Flores,
José C. Monteiro:
Efficient shift-adds design of digit-serial multiple constant multiplications.
ACM Great Lakes Symposium on VLSI 2011: 61-66 |
| 29 |  | Levent Aksoy,
Eduardo Costa,
Paulo F. Flores,
José C. Monteiro:
Design of low-power multiple constant multiplications using low-complexity minimum depth operations.
ACM Great Lakes Symposium on VLSI 2011: 79-84 |
| 28 |  | Levent Aksoy,
Eduardo Costa,
Paulo F. Flores,
José C. Monteiro:
Optimization of gate-level area in high throughput Multiple Constant Multiplications.
ECCTD 2011: 588-591 |
| 27 |  | Levent Aksoy,
Cristiano Lazzari,
Eduardo Costa,
Paulo F. Flores,
José C. Monteiro:
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level.
ISCAS 2011: 2737-2740 |
| 26 |  | Levent Aksoy,
Eduardo Costa,
Paulo F. Flores,
José C. Monteiro:
A hybrid algorithm for the optimization of area and delay in linear DSP transforms.
VLSI-SoC 2011: 148-153 |
| 25 |  | Cristiano Lazzari,
Jorge Fernandes,
Paulo F. Flores,
José Monteiro:
Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays.
J. Low Power Electronics 7(2): 294-301 (2011) |
| 24 |  | Levent Aksoy,
Eduardo Costa,
Paulo F. Flores,
José Monteiro:
Finding the optimal tradeoff between area and delay in multiple constant multiplications.
Microprocessors and Microsystems - Embedded Hardware Design 35(8): 729-741 (2011) |
| 2010 |
| 23 |  | Cristiano Lazzari,
Paulo F. Flores,
José Monteiro,
Luigi Carro:
A new quaternary FPGA based on a voltage-mode multi-valued circuit.
DATE 2010: 1797-1802 |
| 22 |  | Levent Aksoy,
Eduardo Costa,
Paulo F. Flores,
José C. Monteiro:
Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications.
DSD 2010: 3-10 |
| 21 |  | Nuno Sebastião,
Tiago Dias,
Nuno Roma,
Paulo F. Flores:
Integrated accelerator architecture for DNA sequences alignment with enhanced traceback phase.
HPCS 2010: 16-23 |
| 20 |  | Cristiano Lazzari,
Paulo F. Flores,
José Monteiro,
Luigi Carro:
Voltage-mode quaternary FPGAs: An evaluation of interconnections.
ISCAS 2010: 869-872 |
| 19 |  | Cristiano Lazzari,
Jorge Fernandes,
Paulo F. Flores,
José C. Monteiro:
An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs.
PATMOS 2010: 84-93 |
| 18 |  | Diego Jaccottet,
Eduardo Costa,
Levent Aksoy,
Paulo F. Flores,
José C. Monteiro:
Design of low-complexity and high-speed digital Finite Impulse Response filters.
VLSI-SoC 2010: 292-297 |
| 17 |  | Levent Aksoy,
Ece Olcay Günes,
Paulo F. Flores:
Search algorithms for the multiple constant multiplications problem: Exact and approximate.
Microprocessors and Microsystems - Embedded Hardware Design 34(5): 151-162 (2010) |
| 2009 |
| 16 |  | Pedro Marques Morgado,
Paulo F. Flores,
L. Miguel Silveira:
Generating realistic stimuli for accurate power grid analysis.
ACM Trans. Design Autom. Electr. Syst. 14(3): (2009) |
| 15 |  | Luís Gil,
Paulo F. Flores,
Luis Miguel Silveira:
PMSat: a parallel version of MiniSAT.
JSAT 6(1-3): 71-98 (2009) |
| 2008 |
| 14 |  | Nuno Sebastião,
Tiago Dias,
Nuno Roma,
Paulo F. Flores,
Leonel Sousa:
Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units.
DSD 2008: 181-188 |
| 13 |  | Pedro Marques Morgado,
Paulo F. Flores,
José C. Monteiro,
Luis Miguel Silveira:
Generating Worst-Case Stimuli for Accurate Power Grid Analysis.
PATMOS 2008: 247-257 |
| 12 |  | Levent Aksoy,
Eduardo A. C. da Costa,
Paulo F. Flores,
José Monteiro:
Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1013-1026 (2008) |
| 2007 |
| 11 |  | Levent Aksoy,
Eduardo A. C. da Costa,
Paulo F. Flores,
José C. Monteiro:
Optimization of Area in Digital FIR Filters using Gate-Level Metrics.
DAC 2007: 420-423 |
| 10 |  | Pedro Marques Morgado,
Paulo F. Flores,
L. Miguel Silveira:
Generating Realistic Stimuli for Accurate Power Grid Analysis.
ISVLSI 2007: 233-238 |
| 9 |  | Levent Aksoy,
Ece Olcay Günes,
Eduardo A. C. da Costa,
Paulo F. Flores,
José C. Monteiro:
Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications.
SiPS 2007: 424-429 |
| 2006 |
| 8 |  | Levent Aksoy,
Eduardo A. C. da Costa,
Paulo F. Flores,
José Monteiro:
Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming.
DAC 2006: 669-674 |
| 7 |  | Eduardo A. C. da Costa,
Paulo F. Flores,
José Monteiro:
Exploiting general coefficient representation for the optimal sharing of partial products in MCMs.
SBCCI 2006: 161-166 |
| 2005 |
| 6 |  | Paulo F. Flores,
José C. Monteiro,
Eduardo A. C. da Costa:
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications.
ICCAD 2005: 13-16 |
| 2001 |
| 5 |  | Paulo F. Flores,
Horácio C. Neto,
João P. Marques Silva:
An exact solution to the minimum size test pattern problem.
ACM Trans. Design Autom. Electr. Syst. 6(4): 629-644 (2001) |
| 1999 |
| 4 |  | Paulo F. Flores,
Horácio C. Neto,
João P. Marques Silva:
On Applying Set Covering Models to Test Set Compaction.
Great Lakes Symposium on VLSI 1999: 8-11 |
| 3 |  | Paulo F. Flores,
Horácio C. Neto,
K. Chakrabarty,
João P. Marques Silva:
Test pattern generation for width compression in BIST.
ISCAS (1) 1999: 114-118 |
| 2 |  | Paulo F. Flores,
José C. Costa,
Horácio C. Neto,
José C. Monteiro,
João P. Marques Silva:
Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation.
VLSI Design 1999: 37-41 |
| 1997 |
| 1 |  | Vasco M. Manquinho,
Paulo F. Flores,
João P. Marques Silva,
Arlindo L. Oliveira:
Prime Implicant Computation Using Satisfiability Algorithms.
ICTAI 1997: 232-239 |