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José Flich
List of publications from the DBLP Bibliography Server - FAQ
| 2012 | ||
|---|---|---|
| 103 | Francisco Triviño, J. L. Sánchez, Francisco José Alfaro, José Flich: Exploring NoC Virtualization Alternatives in CMPs. PDP 2012: 473-482 | |
| 102 | Jose Flich, Tor Skeie, Andres Mejia, Olav Lysne, Pedro López, Antonio Robles, José Duato, Michihiro Koibuchi, Tomas Rokicki, José Carlos Sancho: A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms. IEEE Trans. Parallel Distrib. Syst. 23(3): 405-425 (2012) | |
| 101 | Carles Hernández, Antoni Roca, Federico Silla, Jose Flich, José Duato: On the Impact of Within-Die Process Variation in GALS-Based NoC Performance. IEEE Trans. on CAD of Integrated Circuits and Systems 31(2): 294-307 (2012) | |
| 2011 | ||
| 100 | Jesus Camacho, Jose Flich: HPC-Mesh: A Homogeneous Parallel Concentrated Mesh for Fault-Tolerance and Energy Savings. ANCS 2011: 69-80 | |
| 99 | Jesus Camacho, José Flich, José Duato, Hans Eberle, Wladek Olesinski: Towards an Efficient NoC Topology through Multiple Injection Ports. DSD 2011: 165-172 | |
| 98 | Francisco Triviño, Francisco José Alfaro, José L. Sánchez, José Flich: A fast centralized computation routing algorithm for self-configuring NoC systems. HiPC 2011: 1-10 | |
| 97 | Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato: A Distributed Switch Architecture for On-Chip Networks. ICPP 2011: 21-30 | |
| 96 | Jesus Camacho, José Flich, Antoni Roca, José Duato: PC-Mesh: A Dynamic Parallel Concentrated Mesh. ICPP 2011: 642-651 | |
| 95 | Jesús Escudero-Sahuquillo, Ernst Gunnar Gran, Pedro Javier García, Jose Flich, Tor Skeie, Olav Lysne, Francisco J. Quiles, José Duato: Combining Congested-Flow Isolation and Injection Throttling in HPC Interconnection Networks. ICPP 2011: 662-672 | |
| 94 | José Flich, Scott Pakin, Craig B. Stunkel: CASS Introduction. IPDPS Workshops 2011: 716-717 | |
| 93 | Francisco Triviño, Francisco José Alfaro, José L. Sánchez, José Flich: NoC Reconfiguration for CMP Virtualization. NCA 2011: 219-222 | |
| 92 | José Cano, José Flich, José Duato, Marcello Coppola, Riccardo Locatelli: Efficient routing implementation in complex systems-on-chip. NOCS 2011: 1-8 | |
| 91 | Florentine Dubois, José Cano, Marcello Coppola, José Flich, Frédéric Pétrot: Spidergon STNoC design flow. NOCS 2011: 267-268 | |
| 90 | José Flich: Switch Architecture. Encyclopedia of Parallel Computing 2011: 1971-1977 | |
| 89 | José Flich: Flow Control. Encyclopedia of Parallel Computing 2011: 683-689 | |
| 88 | Carles Hernández, Antoni Roca, Jose Flich, Federico Silla, José Duato: Fault-Tolerant Vertical Link Design for Effective 3D Stacking. Computer Architecture Letters 10(2): 41-44 (2011) | |
| 87 | Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato: Cost-effective queue schemes for reducing head-of-line blocking in fat-trees. Concurrency and Computation: Practice and Experience 23(17): 2235-2248 (2011) | |
| 86 | Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesus Camacho, Federico Silla, José Duato: Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 30(4): 534-547 (2011) | |
| 85 | Rafael Tornero, Juan Manuel Orduña, Andres Mejia, Jose Flich, José Duato: A Communication-Driven Routing Technique for Application-Specific NoCs. International Journal of Parallel Programming 39(3): 357-374 (2011) | |
| 84 | Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato: OBQA: Smart and cost-efficient queue scheme for Head-of-Line blocking elimination in fat-trees. J. Parallel Distrib. Comput. 71(11): 1460-1472 (2011) | |
| 83 | Carles Hernández, Antoni Roca, José Flich, Federico Silla, José Duato: Characterizing the impact of process variation on 45 nm NoC-based CMPs. J. Parallel Distrib. Comput. 71(5): 651-663 (2011) | |
| 82 | Francisco Triviño, José L. Sánchez, Francisco José Alfaro, José Flich: Virtualizing network-on-chip resources in chip-multiprocessors. Microprocessors and Microsystems - Embedded Hardware Design 35(2): 230-245 (2011) | |
| 81 | Antoni Roca, José Flich, Federico Silla, José Duato: A low-latency modular switch for CMP systems. Microprocessors and Microsystems - Embedded Hardware Design 35(8): 742-754 (2011) | |
| 2010 | ||
| 80 | Antoni Roca, Jose Flich, Federico Silla, José Duato: A Latency-Efficient Router Architecture for CMP Systems. DSD 2010: 165-172 | |
| 79 | José Flich, Alfonso Urso, Ulrich Bruening, Giuseppe Di Fatta: High Performance Networks. Euro-Par (2) 2010: 412 | |
| 78 | Antoni Roca, José Flich, Federico Silla, José Duato: VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks. HiPC 2010: 1-12 | |
| 77 | Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato: Cost-Effective Congestion Management for Interconnection Networks Using Distributed Deterministic Routing. ICPADS 2010: 355-364 | |
| 76 | Scott Pakin, Craig B. Stunkel, Jose Flich, Henrique Andrade, Vibhore Kumar, Deepak S. Turaga: Welcome to CAC/SSPS 2010. IPDPS Workshops 2010: 1 | |
| 75 | Samuel Rodrigo, Jose Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesus Camacho, Federico Silla, José Duato: Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing. NOCS 2010: 25-32 | |
| 74 | Carles Hernández, Antoni Roca, Federico Silla, Jose Flich, José Duato: Improving the Performance of GALS-Based NoCs in the Presence of Process Variation. NOCS 2010: 35-42 | |
| 73 | Teresa Nachiondo Frinós, Jose Flich, José Duato: Buffer Management Strategies to Reduce HoL Blocking. IEEE Trans. Parallel Distrib. Syst. 21(6): 739-753 (2010) | |
| 2009 | ||
| 72 | Vicente Chirivella, Rosa Alcover, Jose Flich, José Duato: Dependability Analysis of a Fault-Tolerant Network Reconfiguring Strategy. Euro-Par 2009: 1040-1051 | |
| 71 | Alejandro Martínez, Pedro Javier García, Francisco José Alfaro, José L. Sánchez, Jose Flich, Francisco J. Quiles, José Duato: A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination. IEEE Trans. Parallel Distrib. Syst. 20(1): 13-24 (2009) | |
| 70 | Andres Mejia, Maurizio Palesi, Jose Flich, Shashi Kumar, Pedro López, Rickard Holsmark, José Duato: Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. IEEE Trans. VLSI Syst. 17(3): 356-369 (2009) | |
| 69 | Samuel Rodrigo, Simone Medardoni, José Flich, Davide Bertozzi, José Duato: Efficient implementation of distributed routing algorithms for NoCs. IET Computers & Digital Techniques 3(5): 460-475 (2009) | |
| 2008 | ||
| 68 | Jose Flich, Samuel Rodrigo, José Duato, Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Olav Lysne: On the Potential of NoC Virtualization for Multicore Chips. CISIS 2008: 801-807 | |
| 67 | Rafael Tornero, Juan Manuel Orduña, Andres Mejia, Jose Flich, José Duato: CART: Communication-Aware Routing Technique for Application-Specific NoCs. DSD 2008: 26-31 | |
| 66 | Tor Skeie, Daniel Ortega, Jose Flich, Raimir Holanda: Topic 13: High-Performance Networks. Euro-Par 2008: 898 | |
| 65 | Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, Jose Flich, José Duato: FBICM: Efficient Congestion Management for High-Performance Networks Using Distributed Deterministic Routing. HiPC 2008: 503-517 | |
| 64 | Andres Mejia, Jose Flich, José Duato: On the Potentials of Segment-Based Routing for NoCs. ICPP 2008: 594-603 | |
| 63 | José Miguel Montañana, Jose Flich, José Duato: Epoch-based reconfiguration: Fast, simple, and effective dynamic network reconfiguration. IPDPS 2008: 1-12 | |
| 62 | Samuel Rodrigo, Jose Flich, José Duato, Mark Hummel: Efficient unicast and multicast support for CMPs. MICRO 2008: 364-375 | |
| 61 | Jose Flich, Samuel Rodrigo, José Duato: An Efficient Implementation of Distributed Routing Algorithms for NoCs. NOCS 2008: 87-96 | |
| 60 | Hans Eberle, Pedro Javier García, Jose Flich, José Duato, Robert Drost, Nils Gura, David Hopkins, Wladek Olesinski: High-radix crossbar switches enabled by proximity communication. SC 2008: 32 | |
| 59 | Olav Lysne, José Miguel Montañana, Jose Flich, José Duato, Timothy Mark Pinkston, Tor Skeie: An Efficient and Deadlock-Free Network Reconfiguration Protocol. IEEE Trans. Computers 57(6): 762-779 (2008) | |
| 58 | José Flich, Samuel Rodrigo, José Duato, Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Olav Lysne: On the Potential of NoC Virtualization for Multicore Chips. Scalable Computing: Practice and Experience 9(3): (2008) | |
| 2007 | ||
| 57 | Alejandro Martínez-Vicente, Pedro Javier García, Francisco José Alfaro, José L. Sánchez, Jose Flich, Francisco J. Quiles, José Duato: Integrated QoS Provision and Congestion Management for Interconnection Networks. Euro-Par 2007: 837-847 | |
| 56 | Gaspar Mora, Pedro Javier García, Jose Flich, José Duato: RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management. ICPP 2007: 74 | |
| 55 | Jose Flich, Andres Mejia, Pedro López, José Duato: Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips. NOCS 2007: 183-194 | |
| 54 | Andres Mejia, Jose Flich, José Duato, Sven-Arne Reinemo, Tor Skeie: Boosting Ethernet Performance by Segment-Based Routing. PDP 2007: 55-62 | |
| 53 | Leticia Pascual, Alejandro Torrentí, Julio Sahuquillo, Jose Flich: Understanding cache hierarchy interactions with a program-driven simulator. WCAE 2007: 30-35 | |
| 52 | José Flich, José Duato: Logic-Based Distributed Routing for NoCs. Computer Architecture Letters 7(1): 13-16 (2007) | |
| 2006 | ||
| 51 | Gaspar Mora, Jose Flich, José Duato, Pedro López, Elvira Baydal, Olav Lysne: Towards an efficient switch architecture for high-radix switches. ANCS 2006: 11-20 | |
| 50 | Alejandro Martínez, Pedro Javier García, Francisco José Alfaro, José L. Sánchez, Jose Flich, Francisco J. Quiles, José Duato: Towards a Cost-Effective Interconnection Network Architecture with QoS and Congestion Management Support. Euro-Par 2006: 884-895 | |
| 49 | Teresa Nachiondo Frinós, Jose Flich, José Duato: Destination-Based HoL Blocking Elimination. ICPADS (1) 2006: 213-222 | |
| 48 | José Miguel Montañana, Jose Flich, Antonio Robles, José Duato: Reachability-Based Fault-Tolerant Routing. ICPADS (1) 2006: 515-524 | |
| 47 | Pedro Javier García, Francisco J. Quiles, Jose Flich, José Duato, Ian Johnson, Finbar Naven: RECN-DD: A Memory-Efficient Congestion Management Technique for Advanced Switching. ICPP 2006: 23-32 | |
| 46 | Andres Mejia, Jose Flich, José Duato, Sven-Arne Reinemo, Tor Skeie: Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and tori. IPDPS 2006 | |
| 45 | Pedro Javier García, Francisco J. Quiles, Jose Flich, José Duato, Ian Johnson, Finbar Naven: Efficient, Scalable Congestion Management for Interconnection Networks. IEEE Micro 26(5): 52-66 (2006) | |
| 44 | María Engracia Gómez, Nils Agne Nordbotten, Jose Flich, Pedro López, Antonio Robles, José Duato, Tor Skeie, Olav Lysne: A Routing Methodology for Achieving Fault Tolerance in Direct Networks. IEEE Trans. Computers 55(4): 400-415 (2006) | |
| 2005 | ||
| 43 | Teresa Nachiondo Frinós, Jose Flich, José Duato, Mitchell Gusat: Cost / Performance Trade-Offs and Fairness Evaluation of Queue Mapping Policies. Euro-Par 2005: 1024-1034 | |
| 42 | Pedro Javier García, Jose Flich, José Duato, Francisco J. Quiles, Ian Johnson, Finbar Naven: On the Correct Sizing on Meshes Through an Effective Congestion Management Strategy. Euro-Par 2005: 1035-1045 | |
| 41 | José Duato, Ian Johnson, Jose Flich, Finbar Naven, Pedro Javier García, Teresa Nachiondo Frinós: A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks. HPCA 2005: 108-119 | |
| 40 | Pedro Javier García, Jose Flich, José Duato, Ian Johnson, Francisco J. Quiles, Finbar Naven: Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture. HiPEAC 2005: 266-285 | |
| 39 | Teresa Nachiondo Frinós, Jose Flich, José Duato: Efficient Reduction of HOL Blocking in Multistage Networks. IPDPS 2005 | |
| 38 | Juan Carlos Martínez, Jose Flich, Antonio Robles, Pedro López, José Duato, Michihiro Koibuchi: In-Order Packet Delivery in Interconnection Networks using Adaptive Routing. IPDPS 2005 | |
| 37 | José Miguel Montañana, José Flich, Antonio Robles, José Duato: A Scalable Methodology for Computing Fault-Free Paths in InfiniBand Torus Networks. ISHPC 2005: 79-92 | |
| 36 | Raúl Martínez, José L. Sánchez, Francisco José Alfaro, Vicente Chirivella, Jose Flich: Studying the Effect of the Design Parameters on the Interconnection Network Performance in NOWs. PDP 2005: 102-109 | |
| 35 | Michihiro Koibuchi, Juan Carlos Martínez, Jose Flich, Antonio Robles, Pedro López, José Duato: Enforcing in-order packet delivery in system area networks with adaptive routing. J. Parallel Distrib. Comput. 65(10): 1223-1236 (2005) | |
| 2004 | ||
| 34 | María Engracia Gómez, José Duato, Jose Flich, Pedro López, Antonio Robles, Nils Agne Nordbotten, Tor Skeie, Olav Lysne: A New Adaptive Fault-Tolerant Routing Methodology for Direct Networks. HiPC 2004: 462-473 | |
| 33 | Olav Lysne, José Miguel Montañana, Timothy Mark Pinkston, José Duato, Tor Skeie, Jose Flich: Simple Deadlock-Free Dynamic Network Reconfiguration. HiPC 2004: 504-515 | |
| 32 | Tor Skeie, Olav Lysne, Jose Flich, Pedro López, Antonio Robles, José Duato: LASH-TOR: A Generic Transition-Oriented Routing Algorithm. ICPADS 2004: 595-604 | |
| 31 | María Engracia Gómez, Jose Flich, Pedro López, Antonio Robles, José Duato, Nils Agne Nordbotten, Olav Lysne, Tor Skeie: An Effective Fault-Tolerant Routing Methodology for Direct Networks. ICPP 2004: 222-231 | |
| 30 | José Miguel Montañana, Jose Flich, Antonio Robles, Pedro López, José Duato: A Transition-Based Fault-Tolerant Routing Methodology for InfiniBand Networks. IPDPS 2004 | |
| 29 | Nils Agne Nordbotten, María Engracia Gómez, Jose Flich, Pedro López, Antonio Robles, Tor Skeie, Olav Lysne, José Duato: A Fully Adaptive Fault-Tolerant Routing Methodology Based on Intermediate Nodes. NPC 2004: 341-356 | |
| 28 | José Duato, Jose Flich, Teresa Nachiondo Frinós: A Cost-Effective Technique to Reduce HOL Blocking in Single-Stage and Multistage Switch Fabrics. PDP 2004: 48-53 | |
| 27 | María Engracia Gómez, José Duato, Jose Flich, Pedro López, Antonio Robles, Nils Agne Nordbotten, Olav Lysne, Tor Skeie: An Efficient Fault-Tolerant Routing Methodology for Meshes and Tori. Computer Architecture Letters 3: (2004) | |
| 26 | Jeffrey M. Stine, Nicholas P. Carter, Jose Flich: Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction. Computer Architecture Letters 3: (2004) | |
| 2003 | ||
| 25 | Pedro López, Jose Flich, Antonio Robles: Low-Fragmentation Mapping Strategies for Linear Forwarding Tables in InfiniBandTM. Euro-Par 2003: 947-957 | |
| 24 | José Carlos Sancho, Antonio Robles, Pedro López, Jose Flich, José Duato: Routing in InfiniBandTM Torus Network Topologie. ICPP 2003: 509-518 | |
| 23 | José Carlos Sancho, Juan Carlos Martínez, Antonio Robles, Pedro López, Jose Flich, José Duato: Performance Evaluation of COWs under Real Parallel Application. IPDPS 2003: 202 | |
| 22 | Juan Carlos Martínez, Jose Flich, Antonio Robles, Pedro López, José Duato: Supporting Fully Adaptive Routing in InfiniBand Networks. IPDPS 2003: 44 | |
| 21 | María Engracia Gómez, Jose Flich, Antonio Robles, Pedro López, José Duato: VOQSW: A Methodology to Reduce HOL Blocking in InfiniBand Networks. IPDPS 2003: 46 | |
| 20 | Juan Carlos Martínez, Jose Flich, Antonio Robles, Pedro López, José Duato: Supporting Adaptive Routing in InfiniBand Networks. PDP 2003: 165-172 | |
| 19 | Jose Flich, Pedro López, Manuel P. Malumbres, José Duato, Tomas Rokicki: Applying In-Transit Buffers to Boost the Performance of Networks with Source Routing. IEEE Trans. Computers 52(9): 1134-1153 (2003) | |
| 18 | Juan Carlos Martínez, Jose Flich, Antonio Robles, Pedro López, José Duato: Supporting adaptive routing in IBA switches. Journal of Systems Architecture 49(10-11): 441-456 (2003) | |
| 2002 | ||
| 17 | María Engracia Gómez, Jose Flich, Antonio Robles, Pedro López, José Duato: Evaluation of Routing Algorithms for InfiniBand Networks (Research Note). Euro-Par 2002: 775-780 | |
| 16 | José Carlos Sancho, Antonio Robles, Jose Flich, Pedro López, José Duato: Effective Methodology for Deadlock-Free Minimal Routing in InfiniBand Networks. ICPP 2002: 409-418 | |
| 15 | José Carlos Sancho, Jose Flich, Antonio Robles, Pedro López, José Duato: Analyzing the Influence of Virtual Lanes on the Performance of InfiniBand Networks. IPDPS 2002 | |
| 14 | Pedro Javier García, M. D. Mora, Francisco José Alfaro, José L. Sánchez, Jose Flich: Evaluation of Alternative Arbitration Policies for Myrinet Switches. IPDPS 2002 | |
| 13 | Jose Flich, Pedro López, José Carlos Sancho, Antonio Robles, José Duato: Improving InfiniBand Routing through Multiple Virtual Networks. ISHPC 2002: 49-63 | |
| 12 | Jose Flich, Manuel P. Malumbres, Pedro López, José Duato: Removing the Latency Overhead of the ITB Mechanism in COWs with Source Routing. PDP 2002: 463-470 | |
| 11 | Jose Flich, Pedro López, Manuel P. Malumbres, José Duato: Boosting the Performance of Myrinet Networks. IEEE Trans. Parallel Distrib. Syst. 13(11): 1166-1182 (2002) | |
| 10 | Jose Flich, Pedro López, Manuel P. Malumbres, José Duato: Boosting the Performance of Myrinet Networks. IEEE Trans. Parallel Distrib. Syst. 13(7): 693-709 (2002) | |
| 2001 | ||
| 9 | Pedro López, Jose Flich, José Duato: Deadlock-Free Routing in InfiniBand through Destination Renaming. ICPP 2001: 427-436 | |
| 8 | Salvador Coll, Jose Flich, Manuel P. Malumbres, Pedro López, José Duato, Francisco J. Mora: A First Implementation of In-Transit Buffers on Myrinet GM Software. IPDPS 2001: 162 | |
| 7 | Jose Flich, Pedro López, Manuel P. Malumbres, José Duato, Tomas Rokicki: Improving Network Performance by Reducing Network Contention in Source-Based COWs with a Low Path-Computation Overhead. IPDPS 2001: 70 | |
| 2000 | ||
| 6 | Jose Flich, Pedro López, Manuel P. Malumbres, José Duato: Improving the Performance of Regular Networks with Source Routing. ICPP 2000: 353-361 | |
| 5 | Jose Flich, Manuel P. Malumbres, Pedro López, José Duato: Performance evaluation of a new routing strategy for irregular networks with source routing. ICS 2000: 34-43 | |
| 4 | Jose Flich, Manuel P. Malumbres, Pedro López, José Duato: Improving Routing Performance in Myrinet Networks. IPDPS 2000: 27-32 | |
| 3 | Jose Flich, Pedro López, Manuel P. Malumbres, José Duato, Tomas Rokicki: Combining In-Transit Buffers with Optimized Routing Schemes to Boost the Performance of Networks with Source Routing. ISHPC 2000: 300-309 | |
| 1999 | ||
| 2 | Jose Flich, Manuel P. Malumbres, Pedro López, José Duato: Performance Evaluation of Networks of Workstations with Hardware Shared Memory Model Using Execution-Driven Simulation. ICPP 1999: 146-153 | |
| 1998 | ||
| 1 | Jose Flich, Pedro López, Manuel P. Malumbres, José Duato: Edinet: An Execution Driven Interconnection Network Simulator for DSM Systems. Computer Performance Evaluation (Tools) 1998: 336-339 | |
Colors in the list of coauthors
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