Edward Flanigan

	2010
9		Edward Flanigan, Spyros Tragoudas: Identification of Delay Measurable PDFs Using Linear Dependency Relationships. IEEE Trans. VLSI Syst. 18(6): 1011-1015 (2010)
	2009
8		Edward Flanigan, Spyros Tragoudas, Arkan Abdulrahman: Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions. VTS 2009: 140-145
	2008
7		Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas: A Novel Test Generation Methodology for Adaptive Diagnosis. ISQED 2008: 242-245
6		Edward Flanigan, Arkan Abdulrahman, Spyros Tragoudas: Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures. ISQED 2008: 633-636
5		Dheepakkumaran Jayaraman, Edward Flanigan, Spyros Tragoudas: Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model. ITC 2008: 1-10
	2007
4		Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas, Michael Laisne, Hailong Cui, Tsvetomir Petrov: Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture. ISQED 2007: 717-722
3		Edward Flanigan, Spyros Tragoudas: Enhanced Identification of Strong Robustly Testable Paths. ISQED 2007: 729-736
2		Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov: Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture. VLSI Design 2007: 805-812
	2006
1		Edward Flanigan, Themistoklis Haniotakis, Spyros Tragoudas: An Improved Method for Identifying Linear Dependencies in Path Delay Faults. ISQED 2006: 457-462

Coauthor Index

1	Arkan Abdulrahman	[6] [8]
2	Rajsekhar Adapa	[2] [4] [7]
3	Hailong Cui	[2] [4]
4	Themistoklis Haniotakis (Th. Haniotakis)	[1]
5	Dheepakkumaran Jayaraman	[5]
6	Michael Laisne	[2] [4]
7	Tsvetomir Petrov	[2] [4]
8	Spyros Tragoudas	[1] [2] [3] [4] [5] [6] [7] [8] [9]

Last update Wed May 30 22:34:44 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page