![]() | ![]() |
| 1993 | ||
|---|---|---|
| 1 | Carlos Delgado Kloos, T. de Miguel Moro, T. Robles Valladares, G. Rabay Filho, Andrés Marín López: VHDL generation from a timed extension of the formal description technique LOTOS within the FORMAT project. Microprocessing and Microprogramming 38(1-5): 589-596 (1993) | |
| 1 | Carlos Delgado Kloos | [1] |
| 2 | Andrés Marín López | [1] |
| 3 | T. de Miguel Moro | [1] |
| 4 | T. Robles Valladares | [1] |
Data released under the ODC-BY 1.0 license — See also our legal information page