Laurent Fesquet

	2012
43		Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet: Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs. DATE 2012: 1325-1330
	2011
42		Chao Yan, Florent Ouchet, Laurent Fesquet, Katell Morin-Allory: Formal Verification of C-element Circuits. ASYNC 2011: 55-64
41		Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet, Alejandro Chagoya: Does asynchronous technology bring robustness in synchronous circuit monitoring? FDL 2011: 1-6
40		Taha Beyrouthy, Laurent Fesquet: An event-driven FIR filter: Design and implementation. International Symposium on Rapid System Prototyping 2011: 59-65
39		Florent Ouchet, Katell Morin-Allory, Laurent Fesquet: C-elements for Hardened Self-timed Circuits. PATMOS 2011: 247-256
38		Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin: A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback CoRR abs/1103.1360: (2011)
	2010
37		Florent Ouchet, Katell Morin-Allory, Laurent Fesquet: Delay Insensitivity Does Not Mean Slope Insensitivity! ASYNC 2010: 176-184
36		Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet: Synthesis of asynchronous monitors for critical electronic systems. DDECS 2010: 329-334
35		Laurent Fesquet, Gilles Sicard, Brigitte Bidégaray-Fesquet: Targeting ultra-low power consumption with non-uniform sampling and filtering. ISCAS 2010: 3585-3588
34		Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet: Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case. PATMOS 2010: 137-149
33		Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet: A high-speed high-resolution low-phase noise oscillator using self-timed rings. VLSI-SoC 2010: 173-178
32		Oussama Elissati, Sébastien Rieubon, Eslam Yahya, Laurent Fesquet: Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks. VLSI-SoC (Selected Papers) 2010: 22-42
31		Laurent Fesquet, Brigitte Bidégaray-Fesquet: IIR digital filtering of non-uniformly sampled signals via state representation. Signal Processing 90(10): 2811-2821 (2010)
	2009
30		Khaled Alsayeg, Katell Morin-Allory, Laurent Fesquet: RAT-based formal verification of QDI asynchronous controllers. FDL 2009: 1-6
29		Eslam Yahya, Laurent Fesquet: Asynchronous design: A promising paradigm for electronic circuits and systems. ICECS 2009: 339-342
28		Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet: Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks. ICECS 2009: 351-354
27		Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin: Adaptive Rate Sampling and Filtering Based on Level Crossing Sampling. EURASIP J. Adv. Sig. Proc. 2009: (2009)
26		Jeremie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin: Constrained Asynchronous Ring Structures for Robust Digital Oscillators. IEEE Trans. VLSI Syst. 17(7): 907-919 (2009)
	2008
25		Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin: Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98
24		Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet: A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks CoRR abs/0809.3942: (2008)
	2007
23		Katell Morin-Allory, Laurent Fesquet, Benjamin Roustan, Dominique Borrione: Asynchronous online-monitoring of logical and temporal assertions. FDL 2007: 286-290
22		Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet: A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. ReCoSoC 2007: 15-22
21		N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin: FPGA Architecture for Multi-Style Asynchronous Logic CoRR abs/0710.4711: (2007)
	2006
20		Katell Morin-Allory, Laurent Fesquet, Dominique Borrione: Asynchronous Assertion Monitors for multi-Clock Domain System Verification. IEEE International Workshop on Rapid System Prototyping 2006: 98-102
19		Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin: State-holding in Look-Up Tables: application to asynchronous logic. VLSI-SoC 2006: 12-17
	2005
18		N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin: FPGA Architecture for Multi-Style Asynchronous Logic. DATE 2005: 32-33
17		D. Borionne, M. Liu, P. Ostier, Laurent Fesquet: PSL-based online monitoring of digital systems. FDL 2005: 465-479
16		Laurent Fesquet, Marc Renaudin: A Programmable Logic Architecture for Prototyping Clockless Circuits. FPL 2005: 293-298
15		Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin: GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. FPL 2005: 299-304
14		Laurent Fesquet, Jerome Quartana, Marc Renaudin: Asynchronous Systems on Programmable Logic. ReCoSoC 2005: 105-112
13		Jerome Quartana, Laurent Fesquet, Marc Renaudin: Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. VLSI-SoC 2005: 195-207
12		Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin: Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. VLSI-SoC 2005: 55-69
	2004
11		F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin: Asynchronous FIR Filters: Towards a New Digital Processing Chain. ASYNC 2004: 198-206
10		Laurent Fesquet, Mohammed Es Salhiene, Marc Renaudin: La technologie asynchrone au service de la réduction d'énergie dans les systèmes embarqués. Annales des Télécommunications 59(7-8): 984-997 (2004)
	2003
9		Emmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin: A New Class of Asynchronous A/D Converters Based on Time Quantization. ASYNC 2003: 196-205
	2002
8		Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana: High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. DATE 2002: 1090
7		Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland: Implementing Asynchronous Circuits on LUT Based FPGAs. FPL 2002: 36-46
6		Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin: Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. IWLS 2002: 191-196
5		Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin: Dynamic Voltage Scheduling for Real Time Asynchronous Systems. PATMOS 2002: 390-399
4		Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard: Low-Power Asynchronous A/D Conversion. PATMOS 2002: 81-91
	2001
3		Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin: Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. VLSI-SOC 2001: 313-324
	1999
2		Wissam Hlayhel, Jacques Henri Collet, Laurent Fesquet: Implementing Snoop-Coherence Protocol for Future SMP Architectures. Euro-Par 1999: 745-752
	1998
1		Wissam Hlayhel, Daniel Litaize, Laurent Fesquet, Jacques Henri Collet: Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures. IEEE PACT 1998: 22-29

Coauthor Index

1	F. Aeschlimann	[11]
2	Emmanuel Allier	[4] [9] [11]
3	Khaled Alsayeg	[30]
4	Alain Aubert	[43]
5	Arnaud Baixas	[15]
6	Taha Beyrouthy	[22] [24] [25] [28] [38] [40]
7	Brigitte Bidégaray-Fesquet (Brigitte Bidégaray)	[31] [35]
8	D. Borionne	[17]
9	Dominique Borrione	[20] [23]
10	Vivian Brégier	[12]
11	Alejandro Chagoya	[41]
12	Sumanta Chaudhuri	[22] [24] [25] [28] [38]
13	Abdelkarim Cherkaoui	[43]
14	Jacques Henri Collet	[1] [2]
15	Jean-Luc Danger	[24] [25] [28] [38]
16	H. Dubreuil	[18] [21]
17	Anh Vu Dihn Duc	[6]
18	Oussama Elissati	[32] [33] [34]
19	Viktor Fischer	[43]
20	Bertrand Folco	[12] [19]
21	Sylvain Guilley	[22] [24] [25] [28] [38]
22	Jeremie Hamon	[26]
23	Wissam Hlayhel	[1] [2]
24	Quoc Thai Ho	[7]
25	Philippe Hoogvorst	[22] [24] [25] [38]
26	N. Huot	[18] [21]
27	Daniel Litaize	[1]
28	M. Liu	[17]
29	Benoit Miscopein	[26]
30	Katell Morin-Allory	[20] [23] [30] [36] [37] [39] [41] [42]
31	P. Ostier	[17]
32	Florent Ouchet	[37] [39] [42]
33	Alexandre Porcher	[36] [41]
34	Saeed Mian Qaisar	[27]
35	Jerome Quartana	[3] [8] [13] [14] [15]
36	Alin Razafindraibe	[22] [25] [38]
37	Salim Renane	[15]
38	Marc Renaudin	[3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [18] [19] [21] [25] [26] [27] [38]
39	Sébastien Rieubon	[32] [33] [34]
40	Jean-Baptiste Rigaud	[3] [7] [8]
41	Robin Rolland	[7]
42	Benjamin Roustan	[23]
43	Mohammed Es Salhiene	[5] [10]
44	Laurent Sauvage	[28]
45	Gilles Sicard	[4] [9] [35]
46	M. Steiner	[19]
47	Eslam Yahya	[29] [32] [33] [34]
48	Chao Yan	[42]

Colors in the list of coauthors

Last update Wed May 30 22:34:44 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page