Klaus Feske

	2002
8		Maik Boden, Jörg Schneider, Klaus Feske, Steffen Rülke: Enhanced Reusability for SoC-Based HW/SW Co-Design. DSD 2002: 94-101
7		Klaus Feske, Georg Heinrich, Berndt Fritzsche, Mark Langer: SoC Based Low Cost Design of Digital Audio Broadcasting Transport Network Applications. FPL 2002: 1105-1109
6		Mirko Benz, Uwe Hatnik, Klaus Feske, Jürgen Haufe: Entwurfsunterstützung zur hardwarebasierten TCP/IP-Beschleunigung (Design Support for Hardware Based TCP/IP Accelerator). it+ti - Informationstechnik und Technische Informatik 44(3): 153-159 (2002)
	2001
5		Mirko Benz, Klaus Feske, Uwe Hatnik, Peter Schwarz: TCP/IP Protocol Engine System Simulation. PROMS 2001: 155-164
	1999
4		Klaus Feske, Michael Scholz, Günther Döring, Denis Nareike: Rapid FPGA Prototyping of a DAB Test Data Generator Using Protocol Compiler. FPL 1999: 243-252
	1998
3		Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske: Multi-Criterial State Assignment for Low Power FSM Design. EUROMICRO 1998: 10261-10268
	1997
2		Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske: Low Power Design of FSMs by State Assignment and Disabling Self-Loops. EUROMICRO 1997: 323-330
1		Klaus Feske, Sven Mulka, Manfred Koegst, Günter Elst: Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs. FPL 1997: 235-244

Coauthor Index

1	Mirko Benz	[5] [6]
2	Maik Boden	[8]
3	Günther Döring	[4]
4	Günter Elst	[1]
5	Günter Franke	[2] [3]
6	Berndt Fritzsche	[7]
7	Uwe Hatnik	[5] [6]
8	Jürgen Haufe	[6]
9	Georg Heinrich	[7]
10	Manfred Koegst	[1] [2] [3]
11	Mark Langer	[7]
12	Sven Mulka	[1]
13	Denis Nareike	[4]
14	Steffen Rülke	[2] [3] [8]
15	Jörg Schneider (Joerg Schneider)	[8]
16	Michael Scholz	[4]
17	Peter Schwarz	[5]

Colors in the list of coauthors

Last update Wed May 30 22:34:44 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page