 | 2008 |
| 12 |  | Péter Szántó,
Gábor Szedö,
Béla Fehér:
High-Performance Timing-Driven Rank Filter.
VLSI Design 2008: (2008) |
| 2005 |
| 11 |  | Mark F. St. John,
Harvey S. Smallman,
Daniel I. Manes,
Béla Fehér,
Jeffrey G. Morrison:
Heuristic Automation for Decluttering Tactical Displays.
Human Factors 47(3): 509-525 (2005) |
| 2004 |
| 10 |  | Péter Szántó,
Béla Fehér:
High performance visibility testing with screen segmentation.
ESTImedia 2004: 75-80 |
| 2003 |
| 9 |  | Régis Leveugle,
Lörinc Antoni,
Béla Fehér:
Dependability Analysis: A New Application for Run-Time Reconfiguration.
IPDPS 2003: 173 |
| 8 |  | Péter Szántó,
Béla Fehér:
3D rendering using FPGAs.
VLSI-SOC 2003: 149-154 |
| 7 |  | Lörinc Antoni,
Régis Leveugle,
Béla Fehér:
Using run-time reconfiguration for fault injection applications.
IEEE T. Instrumentation and Measurement 52(5): 1468-1473 (2003) |
| 2002 |
| 6 |  | Lörinc Antoni,
Régis Leveugle,
Béla Fehér:
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes.
DFT 2002: 245-253 |
| 2000 |
| 5 |  | Lörinc Antoni,
Régis Leveugle,
Béla Fehér:
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes.
DFT 2000: 405-413 |
| 4 |  | Tamás Szabó,
Lörinc Antoni,
Gábor Horváth,
Béla Fehér:
A Full-Parallel Digital Implementation for Pre-Trained NNs.
IJCNN (2) 2000: 49-54 |
| 1998 |
| 3 |  | Béla Fehér,
Gábor Szedö:
Cost Effective 2×2 Inner Product Processors.
FPL 1998: 348-355 |
| 2 |  | Tamás Szabó,
Béla Fehér,
Gábor Horváth:
Neural network implementation using distributed arithmetic.
KES (3) 1998: 510-518 |
| 1993 |
| 1 |  | Béla Fehér:
Efficient synthesis of distributed vector multipliers.
Microprocessing and Microprogramming 38(1-5): 345-350 (1993) |